from soc.fu.alu.alu_input_record import CompALUOpSubset
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
-class ALUInputData(IntegerData):
+class ALUInputData(FUBaseData):
regspec = [('INT', 'ra', '0:63'), # RA
('INT', 'rb', '0:63'), # RB/immediate
('XER', 'xer_so', '32'), # XER bit 32: SO
self.a, self.b = self.ra, self.rb
-class ALUOutputData(IntegerData):
+class ALUOutputData(FUBaseData):
regspec = [('INT', 'o', '0:63'),
('CR', 'cr_a', '0:3'),
('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
op_bctarl CR, TAR, CTR
"""
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace
-class BranchInputData(IntegerData):
+class BranchInputData(FUBaseData):
# Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
# this involves the *decode* unit selecting the register, based
# on detecting the operand being bcctr, bclr or bctar
self.cr = self.cr_a
-class BranchOutputData(IntegerData):
+class BranchOutputData(FUBaseData):
regspec = [('FAST', 'fast1', '0:63'),
('FAST', 'fast2', '0:63'),
('STATE', 'nia', '0:63')]
Links:
* https://libre-soc.org/3d_gpu/architecture/regfile/ section on regspecs
"""
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
from soc.fu.cr.cr_input_record import CompCROpSubset
-class CRInputData(IntegerData):
+class CRInputData(FUBaseData):
regspec = [('INT', 'ra', '0:63'), # 64 bit range
('INT', 'rb', '0:63'), # 64 bit range
('CR', 'full_cr', '0:31'), # 32 bit range
self.a, self.b = self.ra, self.rb
-class CROutputData(IntegerData):
+class CROutputData(FUBaseData):
regspec = [('INT', 'o', '0:63'), # RA - 64 bit range
('CR', 'full_cr', '0:31'), # 32 bit range
('CR', 'cr_a', '0:3')] # 4 bit range
import enum
from nmigen import Signal, Const
-from soc.fu.pipe_data import IntegerData
+from soc.fu.pipe_data import FUBaseData
from soc.fu.alu.pipe_data import CommonPipeSpec
from soc.fu.logical.logical_input_record import CompLogicalOpSubset
from ieee754.div_rem_sqrt_rsqrt.core import (
DivPipeCoreSetupStage, DivPipeCoreCalculateStage, DivPipeCoreFinalStage)
-class DivInputData(IntegerData):
+class DivInputData(FUBaseData):
regspec = [('INT', 'ra', '0:63'), # RA
('INT', 'rb', '0:63'), # RB/immediate
('XER', 'xer_so', '32'), ] # XER bit 32: SO
# output stage shared between div and mul: like ALUOutputData but no CA/32
-class DivMulOutputData(IntegerData):
+class DivMulOutputData(FUBaseData):
regspec = [('INT', 'o', '0:63'),
('CR', 'cr_a', '0:3'),
('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32
from soc.fu.ldst.ldst_input_record import CompLDSTOpSubset
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
-class LDSTInputData(IntegerData):
+class LDSTInputData(FUBaseData):
regspec = [('INT', 'ra', '0:63'), # RA
('INT', 'rb', '0:63'), # RB/immediate
('INT', 'rc', '0:63'), # RC
self.rs = self.rc
-class LDSTOutputData(IntegerData):
+class LDSTOutputData(FUBaseData):
regspec = [('INT', 'o', '0:63'), # RT
('INT', 'o1', '0:63'), # RA (effective address, update mode)
# TODO, later ('CR', 'cr_a', '0:3'),
-from soc.fu.pipe_data import IntegerData
+from soc.fu.pipe_data import FUBaseData
from soc.fu.alu.pipe_data import ALUOutputData, CommonPipeSpec
from soc.fu.logical.logical_input_record import CompLogicalOpSubset
# input (and output) for logical initial stage (common input)
-class LogicalInputData(IntegerData):
+class LogicalInputData(FUBaseData):
regspec = [('INT', 'ra', '0:63'), # RA
('INT', 'rb', '0:63'), # RB/immediate
('XER', 'xer_so', '32'), # bit0: so
# input to logical final stage (common output)
-class LogicalOutputData(IntegerData):
+class LogicalOutputData(FUBaseData):
regspec = [('INT', 'o', '0:63'), # RT
('CR', 'cr_a', '0:3'),
('XER', 'xer_so', '32'), # bit0: so
# output from logical final stage (common output) - note that XER.so
# is *not* included (the only reason it's in the input is because of CR0)
-class LogicalOutputDataFinal(IntegerData):
+class LogicalOutputDataFinal(FUBaseData):
regspec = [('INT', 'o', '0:63'), # RT
('CR', 'cr_a', '0:3'),
]
* https://libre-soc.org/3d_gpu/architecture/regfile/
"""
-from soc.fu.pipe_data import IntegerData
+from soc.fu.pipe_data import FUBaseData
from soc.fu.mmu.mmu_input_record import CompMMUOpSubset
from soc.fu.alu.pipe_data import CommonPipeSpec
-class MMUInputData(IntegerData):
+class MMUInputData(FUBaseData):
regspec = [('INT', 'ra', '0:63'), # RA
('INT', 'rb', '0:63'), # RB
('SPR', 'spr1', '0:63'), # MMU (slow)
self.b = self.rb
-class MMUOutputData(IntegerData):
+class MMUOutputData(FUBaseData):
regspec = [('INT', 'o', '0:63'), # RT
('SPR', 'spr1', '0:63'), # MMU (slow)
]
from soc.fu.mul.mul_input_record import CompMULOpSubset
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
from soc.fu.div.pipe_data import DivInputData, DivMulOutputData
from nmigen import Signal
self.data.append(self.neg_res32)
-class MulOutputData(IntegerData):
+class MulOutputData(FUBaseData):
regspec = [('INT', 'o', '0:128'),
('XER', 'xer_so', '32')] # XER bit 32: SO
def __init__(self, pspec):
from soc.fu.regspec import get_regspec_bitwidth
-class IntegerData:
- """IntegerData: base class for all pipeline data structures
+class FUBaseData:
+ """FUBaseData: base class for all pipeline data structures
see README.md for explanation of parameters and purpose.
(repr(self), repr(i), repr(self.data), repr(i.data))
for j in range(len(self.data)):
assert type(self.data[j]) == type(i.data[j]), \
- "type mismatch in IntegerData %s %s" % \
+ "type mismatch in FUBaseData %s %s" % \
(repr(self.data[j]), repr(i.data[j]))
eqs.append(self.data[j].eq(i.data[j]))
return eqs
from soc.fu.shift_rot.sr_input_record import CompSROpSubset
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
from soc.fu.alu.pipe_data import ALUOutputData
-class ShiftRotInputData(IntegerData):
+class ShiftRotInputData(FUBaseData):
regspec = [('INT', 'ra', '0:63'), # RA
('INT', 'rb', '0:63'), # RB
('INT', 'rc', '0:63'), # RS
# input to shiftrot final stage (common output)
-class ShiftRotOutputData(IntegerData):
+class ShiftRotOutputData(FUBaseData):
regspec = [('INT', 'o', '0:63'), # RT
('CR', 'cr_a', '0:3'),
('XER', 'xer_so', '32'), # bit0: so
# output from shiftrot final stage (common output) - note that XER.so
# is *not* included (the only reason it's in the input is because of CR0)
-class ShiftRotOutputDataFinal(IntegerData):
+class ShiftRotOutputDataFinal(FUBaseData):
regspec = [('INT', 'o', '0:63'), # RT
('CR', 'cr_a', '0:3'),
('XER', 'xer_ca', '34,45'), # XER bit 34/45: CA/CA32
* https://libre-soc.org/3d_gpu/architecture/regfile/
"""
-from soc.fu.pipe_data import IntegerData
+from soc.fu.pipe_data import FUBaseData
from soc.fu.spr.spr_input_record import CompSPROpSubset
from soc.fu.alu.pipe_data import CommonPipeSpec
-class SPRInputData(IntegerData):
+class SPRInputData(FUBaseData):
regspec = [('INT', 'ra', '0:63'), # RA
('SPR', 'spr1', '0:63'), # SPR (slow)
('FAST', 'fast1', '0:63'), # SPR (fast: LR, CTR etc)
self.a = self.ra
-class SPROutputData(IntegerData):
+class SPROutputData(FUBaseData):
regspec = [('INT', 'o', '0:63'), # RT
('SPR', 'spr1', '0:63'), # SPR (slow)
('FAST', 'fast1', '0:63'), # SPR (fast: LR, CTR etc)
-from soc.fu.pipe_data import IntegerData, CommonPipeSpec
+from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
from soc.fu.trap.trap_input_record import CompTrapOpSubset
-class TrapInputData(IntegerData):
+class TrapInputData(FUBaseData):
regspec = [('INT', 'ra', '0:63'), # RA
('INT', 'rb', '0:63'), # RB/immediate
('FAST', 'fast1', '0:63'), # SRR0
self.a, self.b = self.ra, self.rb
-class TrapOutputData(IntegerData):
+class TrapOutputData(FUBaseData):
regspec = [('INT', 'o', '0:63'), # RA
('FAST', 'fast1', '0:63'), # SRR0 SPR
('FAST', 'fast2', '0:63'), # SRR1 SPR
projects / soc.git / commitdiff