Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / config /
2023-09-11 Jacob Lifshaymark test_pi2ls.py as broken
2022-07-06 Luke Kenneth Casso... update pinmux submodule, rename to "fabric"
2022-01-09 Luke Kenneth Casso... add linux-5.7 unit test which showed a silly error:
2021-12-13 Tobias Platenuse NamedTuple pr in test_pi2ls
2021-12-13 Tobias Platenadd signals to port interface as descibed in bug 756
2021-12-12 Luke Kenneth Casso... in a terrible botched way, get at I-Cache and set it up
2021-12-11 Luke Kenneth Casso... fix bug in unit test, forgot that wb_get mem dict is...
2021-12-11 Luke Kenneth Casso... whoops forgot to add pspec
2021-12-11 Luke Kenneth Casso... connect up I-Cache to FetchUnitInterface
2021-12-11 Luke Kenneth Casso... add new ConfigFetchUnit option "mmu_cache_wb" which...
2021-12-09 Luke Kenneth Casso... add I-Cache to FSM local variables
2021-12-04 Tobias Platenfixed wait_addr to exit immediately on exception
2021-12-04 Luke Kenneth Casso... remove DAR from PortInterface (where is the data going...
2021-12-04 Luke Kenneth Casso... fix pi_st which should not be trying to wait for the...
2021-12-03 Luke Kenneth Casso... fix up LDST test functions pi_ld and pi_st to respect...
2021-12-03 Luke Kenneth Casso... whitespace
2021-12-02 Tobias Platenfix test_random in test_loadstore1
2021-11-24 Tobias Platenfix exception handling in pi_ld
2021-11-22 Tobias Platenfix fast exception handling for pi_st
2021-11-21 Tobias Platenadd testcase for fast exceptions on store
2021-11-20 Tobias Platenfix pi_ld testcase
2021-11-17 Tobias Platenwhitespace
2021-11-17 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-11-17 Tobias Platenfix mistake in test_pi2ls.py
2021-11-17 Tobias Platenfixed busy waiting in pi_st
2021-11-16 Tobias Platenpi_ld busy waiting fix
2021-11-13 Luke Kenneth Casso... add quick instructions on how to run pinouts.py to...
2021-11-13 Luke Kenneth Casso... add new get_pinspec_resources function which creates...
2021-11-13 Luke Kenneth Casso... code-comment for get_pinspecs()
2021-10-08 Luke Kenneth Casso... Merge branch 'pr' from nix-soc
2021-10-08 Tobias Platenwhitespace
2021-10-08 Tobias Platenremove redunant pi_dcbz
2021-10-08 Tobias Platendcbz symbol rename
2021-10-03 Tobias Platenwhitespace
2021-10-03 Tobias Platenremove redunant pi_dcbz
2021-10-02 Tobias Platendcbz symbol rename
2021-09-25 Las SafinMerge remote-tracking branch 'upstream/master' into pr
2021-09-16 Las SafinSplit up into several derivations
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2021-07-21 Tobias Platenrevert accidential delete in test_pi2ls.py causing...
2021-07-21 Tobias Platenupdate pi_dcbz function
2021-07-19 Tobias Platensrc/soc/config/test/test_pi2ls.py: add more debug outputs
2021-07-11 Tobias Platenimplement pi_dcbz
2021-05-25 Tobias Platenwait_ldok: add debug output count
2021-05-14 Luke Kenneth Casso... sort out LoadStore1 misalignment FSM, also required...
2021-05-12 Luke Kenneth Casso... start doing virtual memory queries via PortInterface...
2021-04-30 Luke Kenneth Casso... add a TestSRAM variant of LoadStore1, for being able...
2021-04-30 Luke Kenneth Casso... set up LoadStore1 in ConfigMemoryPortInterface and...
2021-04-23 Luke Kenneth Casso... removing more as moved over to openpower-isa
2021-04-01 Luke Kenneth Casso... use OrderedDict to restore exact order from JSON file
2021-02-26 Luke Kenneth Casso... comment on CoreState
2021-02-15 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-14 Luke Kenneth Casso... add SVSTATE to CoreState
2020-10-04 Luke Kenneth Casso... significant reorg of the litex pinspecs to use pinmux...
2020-10-04 Luke Kenneth Casso... submodule update
2020-09-06 Luke Kenneth Casso... add DEC SPR to CoreState and PowerDecoder, activate...
2020-09-04 Luke Kenneth Casso... adding option to include XICS external interrupts.
2020-08-21 Luke Kenneth Casso... ld/st bus reduction test operational
2020-08-21 Luke Kenneth Casso... first test of down-converted load/store from 64 to...
2020-08-03 Luke Kenneth Casso... use new soc.config.state CoreState class in DMI and...
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-29 Jacob Lifshayclean up some tests
2020-07-29 Jacob Lifshayformat some tests
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-15 Luke Kenneth Casso... add better comments on mul overflow
2020-07-15 Luke Kenneth Casso... test privileged rfid call
2020-07-11 Luke Kenneth Casso... add bigendian mode to helloworld test
2020-07-11 Luke Kenneth Casso... sort out big/little endian startup on qemu
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-07 Luke Kenneth Casso... code-shuffle on testing to prepare loading large files...
2020-07-02 Luke Kenneth Casso... use Mock class (more convenient)
2020-07-02 Luke Kenneth Casso... add bare wishbone option to TestIssuer, sort out ports
2020-07-01 Luke Kenneth Casso... minor reorg on how Bus and Config classes are set up
2020-06-29 Luke Kenneth Casso... fetch instructions from bare wishbone fetch unit
2020-06-28 Luke Kenneth Casso... add Config Fetch interface and quick unit test
2020-06-27 Luke Kenneth Casso... unit test in l0_cache to connect to testpi and test_bare_wb
2020-06-27 Luke Kenneth Casso... fix TestMemLoadStoreUnit, it required a FSM to monitor...
2020-06-27 Luke Kenneth Casso... add wishbone Pi2LSUI test
2020-06-27 Luke Kenneth Casso... reconfigureable PortInterface testing now possible
2020-06-26 Luke Kenneth Casso... load/store unit test needed to wait for busy_o
2020-06-26 Luke Kenneth Casso... investigating why write-enable not getting passed through
2020-06-26 Luke Kenneth Casso... whoops forgot to call parent elaborate
2020-06-26 Luke Kenneth Casso... add test of SRAM through wishbone bus
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-26 Luke Kenneth Casso... add a test SRAM that lives behind a minerva LoadStoreUn...
2020-06-26 Luke Kenneth Casso... add reconfigureable Load/Store class