2021-12-06 |
Luke Kenneth Casso... | convert DTLBUpdate to use a pair of Memorys |
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2021-12-06 |
Luke Kenneth Casso... | more signals local to DTLBUpdate |
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2021-12-06 |
Luke Kenneth Casso... | more signals local to DTLBUpdate |
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2021-12-06 |
Luke Kenneth Casso... | update DTLBUpdate to reflect internal API now |
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2021-12-06 |
Luke Kenneth Casso... | ooo nasty bug. used tlb_hit.way instead of tlb_hit... |
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2021-12-06 |
Luke Kenneth Casso... | move DTLB Tags/Valids/PTEs into DTLBUpdate module |
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2021-12-06 |
Luke Kenneth Casso... | start moving TLBArray into DTLBUpdate |
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2021-12-06 |
Luke Kenneth Casso... | PLRUs were selecting an output index, only one selected |
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2021-12-06 |
Luke Kenneth Casso... | repeated copies of read/write addr/sel to Cache SRAMs |
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2021-12-06 |
Luke Kenneth Casso... | move bank of PLRUs to their own submodule in both dcach... |
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2021-12-06 |
Luke Kenneth Casso... | code-comments |
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2021-12-06 |
Luke Kenneth Casso... | use binary-to-unary encoders in dcache.py |
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2021-12-06 |
Luke Kenneth Casso... | global (one) do_read signal in cache_rams dcache.py |
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2021-12-06 |
Luke Kenneth Casso... | use one-hot binary-to-unary in dcache.py |
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2021-12-05 |
Luke Kenneth Casso... | use unary encoding (one-hot) for replace_way hit_way... |
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2021-12-05 |
Luke Kenneth Casso... | whitespace and minor cleanup of D-Cache |
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2021-12-05 |
Luke Kenneth Casso... | more use of TLBHit Record in D-Cache |
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2021-12-05 |
Luke Kenneth Casso... | correct tlb_hit_way and index sizes, use TLBHit Record... |
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2021-12-05 |
Luke Kenneth Casso... | use TLBRecord in D-Cache for which TLB is selected |
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2021-12-05 |
Luke Kenneth Casso... | split out TLBRecord, correct number of valid bits |
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2021-12-05 |
Luke Kenneth Casso... | use Record in DCache for TLB |
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2021-12-05 |
Luke Kenneth Casso... | use Record in D-Cache Cache Tags |
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2021-12-05 |
Luke Kenneth Casso... | fix icache row store issue |
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2021-12-05 |
Luke Kenneth Casso... | wishbone bus convert on dcache |
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2021-11-11 |
Luke Kenneth Casso... | invert numbering on CR HDLState.get_crregs |
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2021-08-24 |
Luke Kenneth Casso... | big rename, global/search/replace of ready_o with o_rea... |
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2021-07-14 |
Tobias Platen | dcache: improve debug output |
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2021-06-20 |
Tobias Platen | dcache: add debug output |
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2021-05-13 |
Luke Kenneth Casso... | yet more debug log stuff for DCache, this time on Cache... |
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2021-05-13 |
Luke Kenneth Casso... | ha, hilarious: swapped TLBUpdate output sizes db_out... |
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2021-05-13 |
Luke Kenneth Casso... | whoops TLBIE must *clear* the valid bit not set it... |
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2021-05-13 |
Luke Kenneth Casso... | more debug Display in dcache.py |
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2021-05-13 |
Luke Kenneth Casso... | putting in a lot more debug print statements in DCache... |
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2021-05-12 |
Luke Kenneth Casso... | move dcache unit test to separate test_dcache.py |
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2021-05-10 |
Luke Kenneth Casso... | whoops, indentation issue on m.If/m.Else in dcache.py |
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2021-05-10 |
Luke Kenneth Casso... | add links to set associative image, and bugreport |
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2021-05-02 |
Luke Kenneth Casso... | add nc argument to dcache load/store tests |
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2021-05-02 |
Luke Kenneth Casso... | quick hack to SRAM test and to dcache to enable classic... |
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2021-05-01 |
Luke Kenneth Casso... | dcache store test: data goes in one cycle AFTER valid... |
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2021-05-01 |
Cesar Strauss | Add GTKWave documents to each DCache unit test |
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2021-04-26 |
Luke Kenneth Casso... | simple regression dcache test was faulty. wishbone... |
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2021-04-26 |
Luke Kenneth Casso... | incorrect indentation in dcache rams |
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2021-04-26 |
Luke Kenneth Casso... | simplify dcache test |
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2021-04-25 |
Luke Kenneth Casso... | spelling mistake |
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2021-04-25 |
Luke Kenneth Casso... | remove RegStage1.real_adr temporary from dcache |
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2021-04-25 |
Luke Kenneth Casso... | do not overwrite parameter ra in dcache |
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2021-04-25 |
Luke Kenneth Casso... | comment out dcache_store from test, not the problem |
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2021-04-25 |
Luke Kenneth Casso... | remove unneeded code |
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2021-04-25 |
Luke Kenneth Casso... | read req in wb_in.stall, dcache |
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2021-04-25 |
Luke Kenneth Casso... | add single regression test for dcache |
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2021-04-25 |
Luke Kenneth Casso... | add TODO comment in dcache |
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2021-04-25 |
Luke Kenneth Casso... | move Signals in dcache to relevant context |
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2021-04-25 |
Luke Kenneth Casso... | dcache Elif used where If should have been |
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2021-04-25 |
Luke Kenneth Casso... | whoops should be cyc & ~ack |
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2021-04-25 |
Luke Kenneth Casso... | hard-code dcache stall signal to non-pipelined mode |
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2021-04-24 |
Luke Kenneth Casso... | increase memory size in dcache test |
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2021-04-24 |
Luke Kenneth Casso... | increase size of random dcache testing by 10 |
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2021-04-24 |
Luke Kenneth Casso... | fix errors in dcache unit test |
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2021-04-22 |
Luke Kenneth Casso... | add debugging and buffering to CacheRam |
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2021-04-22 |
Luke Kenneth Casso... | whitespace |
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2021-04-22 |
Luke Kenneth Casso... | r1.end_row_ix off-by-one in dcache |
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2021-04-22 |
Luke Kenneth Casso... | sync missing in dcache |
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2021-04-22 |
Luke Kenneth Casso... | dcache.py code-comments |
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2021-04-22 |
Luke Kenneth Casso... | cleanup dcache |
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2021-04-22 |
Luke Kenneth Casso... | error using sync, should have been comb |
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2021-04-21 |
Luke Kenneth Casso... | experimenting with dcache |
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2021-04-20 |
Luke Kenneth Casso... | use soc.bus.sram instead of nmigen_soc.wishbone.sram |
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2020-12-13 |
Cesar Strauss | Allow more test cases to be run with CXXSim |
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2020-10-05 |
Luke Kenneth Casso... | add debug / investigation print statements |
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2020-10-01 |
Luke Kenneth Casso... | arg CacheRam read output needs delay by 1 cycle |
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2020-10-01 |
Luke Kenneth Casso... | do not pass cache row array around, just the current row |
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2020-09-14 |
Luke Kenneth Casso... | increase TLB_NUM_WAYS to 4 |
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2020-09-14 |
Luke Kenneth Casso... | add array signal names |
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2020-09-14 |
Luke Kenneth Casso... | rename plru input |
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2020-09-14 |
Luke Kenneth Casso... | rename plru input |
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2020-09-14 |
Luke Kenneth Casso... | TLB PLRUs are of TLB_WAY_BITS width |
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2020-09-14 |
Luke Kenneth Casso... | fix mmu perms/lookup in dcache |
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2020-09-13 |
Luke Kenneth Casso... | dcache truncate wishbone address, store real_addr in... |
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2020-09-13 |
Luke Kenneth Casso... | MMU test |
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2020-09-13 |
Luke Kenneth Casso... | sort out ariane PLRU, rename/clarify |
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2020-09-13 |
Luke Kenneth Casso... | rename cache_valid_bits to cache_validsg |
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2020-09-13 |
Luke Kenneth Casso... | cache_valid_idx too large in dcache |
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2020-09-13 |
Luke Kenneth Casso... | whoops, cache valid array too small in dcache |
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2020-09-12 |
Luke Kenneth Casso... | more dcache debugging |
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2020-09-12 |
Luke Kenneth Casso... | missing reservation address comparison |
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2020-09-12 |
Luke Kenneth Casso... | dcache tidyup |
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2020-09-12 |
Luke Kenneth Casso... | more dcache debugging |
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2020-09-12 |
Luke Kenneth Casso... | add random dcache mem test |
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2020-09-12 |
Luke Kenneth Casso... | cache valid corrupted: fixed |
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2020-09-12 |
Luke Kenneth Casso... | adding names to array signals |
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2020-09-12 |
Luke Kenneth Casso... | whoops, indentation error |
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2020-09-12 |
Luke Kenneth Casso... | enable Display debugs |
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2020-09-12 |
Luke Kenneth Casso... | set bytesel in dcache store |
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2020-09-11 |
Luke Kenneth Casso... | separat stbs_done into ld/st |
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2020-09-11 |
Luke Kenneth Casso... | dcache load/store test |
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2020-09-11 |
Luke Kenneth Casso... | debugging dcache |
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2020-09-11 |
Luke Kenneth Casso... | connect up WB SRAM to dcache test |
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2020-09-11 |
Luke Kenneth Casso... | start on dcache test |
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2020-09-11 |
Luke Kenneth Casso... | missing comb += |
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2020-09-11 |
Luke Kenneth Casso... | missing maybe_tlb_plrus |
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