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sort out misaligned store in LoadStore1
[soc.git]
/
src
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soc
/
experiment
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test
/
test_loadstore1.py
2022-01-28
Luke Kenneth Casso...
sort out misaligned store in LoadStore1
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2022-01-08
Luke Kenneth Casso...
fix MMU lookup after 2nd request (misaligned) by also...
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2022-01-08
Luke Kenneth Casso...
add microwatt mmu.bin test5 to show page-fault on misal...
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2022-01-08
Luke Kenneth Casso...
enable microwatt mmu test2
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2022-01-08
Luke Kenneth Casso...
whitespace and use exc is None not exc == None
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2022-01-08
Tobias Platen
add function test_pi_ld_misalign
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2022-01-07
Tobias Platen
begin testcase for misalign
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2022-01-07
Luke Kenneth Casso...
whitespace
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2021-12-25
Luke Kenneth Casso...
add mmu.bin test2 to much simpler test_loadstore1.py
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2021-12-25
Luke Kenneth Casso...
move msr in test_loadstore1.py outside of conditional...
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2021-12-25
Luke Kenneth Casso...
whitespace
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2021-12-14
Tobias Platen
test_loadstore1.py: test_loadstore1_ifetch_multi now...
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2021-12-14
Tobias Platen
fix test_loadstore1_ifetch_multi() in test_loadstore1.py
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2021-12-14
Tobias Platen
wip test case for virtual address fetch using fetch...
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2021-12-14
Tobias Platen
fix test_loadstore1_ifetch_multi()
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2021-12-13
Tobias Platen
try to get multi test running
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2021-12-13
Tobias Platen
comments about test_loadstore1_ifetch()
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2021-12-13
Luke Kenneth Casso...
fix test_loadstore1.py with MSR=PR/DR
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2021-12-13
Luke Kenneth Casso...
add in missing MSRSpec import
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2021-12-13
Luke Kenneth Casso...
commented-out code
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2021-12-13
Luke Kenneth Casso...
pass in new MSRSpec to test_loadstore1.py not msr_pr=1
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2021-12-13
Tobias Platen
more work on test_loadstore1_ifetch_multi()
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2021-12-11
Luke Kenneth Casso...
fix bug in unit test, forgot that wb_get mem dict is...
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2021-12-11
Luke Kenneth Casso...
get FetchUnitInterface I-Cache test working (sort-of)
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2021-12-11
Luke Kenneth Casso...
comment out broken test
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2021-12-11
Tobias Platen
typo fix, add missing stop statement to _test_loadstore...
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2021-12-11
Tobias Platen
add loop with multiple instructions for testing
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2021-12-11
Tobias Platen
add skeleton for test_loadstore1_ifetch_multi()
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2021-12-11
Luke Kenneth Casso...
add start of test_loadstore1_ifetch_unit_interface()
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2021-12-10
Tobias Platen
use icache_read in one place
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2021-12-10
Tobias Platen
test_loadstore1.py: begin code deduplication
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2021-12-09
Luke Kenneth Casso...
add some examination of the failed-fetched instruction
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2021-12-09
Luke Kenneth Casso...
add some debug string info to gtkwave
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2021-12-09
Tobias Platen
implement main part of test_loadstore1_ifetch_invalid()
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2021-12-09
Tobias Platen
cleanup test_loadstore1.py
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2021-12-08
Luke Kenneth Casso...
add special pagetable to ifetch_invalid with execute...
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2021-12-08
Luke Kenneth Casso...
do not try priv_mode on the instruction fetch (not...
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2021-12-08
Tobias Platen
begin working on _test_loadstore1_ifetch_invalid()...
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2021-12-08
Tobias Platen
more work on test_loadstore1_ifetch_invalid()
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2021-12-08
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-12-08
Tobias Platen
add skeleton for test_loadstore1_ifetch_invalid()
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2021-12-08
Luke Kenneth Casso...
check that no exception occurs in the virtual-memory...
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2021-12-08
Luke Kenneth Casso...
make LoadStore1 intsr_fault a "captured flag" - strictl...
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2021-12-08
Luke Kenneth Casso...
add instr_fault to LoadStore1 FSM
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2021-12-07
Luke Kenneth Casso...
complete the i-cache fetch through the MMU, including...
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2021-12-07
Luke Kenneth Casso...
set separate "iside" signal in LoadStore1 to not confuse it
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2021-12-07
Luke Kenneth Casso...
start extending icache loadstore test
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2021-12-07
Luke Kenneth Casso...
add first i-cache fetch (non-virtual), no MMU lookup...
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2021-12-07
Luke Kenneth Casso...
code-comments
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2021-12-07
Luke Kenneth Casso...
add in I-Cache into LoadStore1 - presently unused ...
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2021-12-05
Luke Kenneth Casso...
wishbone bus convert on dcache
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2021-12-04
Luke Kenneth Casso...
should not have been duplicating wb_get function in...
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2021-12-04
Luke Kenneth Casso...
remove DAR from PortInterface (where is the data going...
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2021-12-04
Luke Kenneth Casso...
stop using dar_o from PortInterface, get DAR directly...
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2021-12-03
Luke Kenneth Casso...
fix up test_loadstore1.py
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2021-12-02
Tobias Platen
fix test_random in test_loadstore1
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2021-11-30
Tobias Platen
random loadstore1 test: readback written data
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2021-11-30
Tobias Platen
reenable dcbz test case
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2021-11-30
Tobias Platen
cleanup test_loadstore1.py
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2021-11-30
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-11-28
Tobias Platen
update loadstore1 testcase
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2021-11-27
Tobias Platen
loadstore testcase: read at random addresses
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2021-11-25
Tobias Platen
seperate invalid test case from other test cases
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2021-11-25
Tobias Platen
add testcase for invalid pagetable
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2021-11-23
Tobias Platen
fix test_loadstore1.py
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2021-11-22
Tobias Platen
add store testcase
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2021-11-20
Tobias Platen
fix pi_ld testcase
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2021-11-19
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2021-11-18
Tobias Platen
more work on test_loadstore1
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2021-11-16
Tobias Platen
pi_ld busy waiting fix
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2021-11-16
Tobias Platen
loadstore1 now reports exception reason
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2021-11-15
Tobias Platen
report dar on exception + test case
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2021-11-15
Tobias Platen
add test_loadstore1.py
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