Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
[soc.git] / src / soc / experiment / test /
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 Tobias Platentestcase: add mmu, link mmu and dcache together
2021-09-21 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-21 Tobias Platencomment out lines that cause test_compldst_multi_mmu...
2021-09-20 Tobias Platenupdate test_compldst_multi_mmu.py
2021-09-19 Cesar StraussReplace "Display" with "print" on simulation process
2021-09-15 isengaaraMerge branch 'master' of ssh://git.libre-riscv.org...
2021-09-15 isengaaraadd new testcase for ompldst_multi using mmu
2021-08-24 Luke Kenneth Casso... big rename, global/search/replace of ready_o with o_rea...
2021-08-01 Jonathan NeuschäferRename test_dcache, which can't be invoked by test...
2021-07-23 Tobias Platentest_dcbz_pi.py: dcbz now working
2021-07-21 Tobias Platentest_dcbz_pi.py: do not use problem state
2021-07-19 Tobias Platentest_dcbz_pi.py: more work on unit test
2021-07-14 Tobias Platenadd more debug outputs, pass dcbz to loadstore/dcache
2021-07-11 Tobias Platenmore work on test_dcbz_pi.py
2021-07-11 Tobias Platenimplement pi_dcbz
2021-07-11 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-07-11 Tobias Platenadd test_dcbz_pi.py (skeleton only)
2021-07-10 Cesar StraussAdd new traces to the GTKWave document
2021-07-10 Cesar StraussAdd operand producers to the parallel LDST Compunit...
2021-07-10 Cesar StraussDetect unexpected operand fetches and produced results
2021-07-07 Cesar StraussStart of a GTKWave document for the LDST CompUnit paral...
2021-07-04 Cesar StraussBeginning of a class to make a parallel test case for...
2021-06-30 Tobias Platencut down on time by uncommenting data not needed, addin...
2021-06-28 Tobias Platenupdate ldst test case by adding precise timing
2021-06-20 Tobias Platenupdate test_ldst_pi.py
2021-06-18 Tobias Platenuncomment test_dcache_random
2021-06-14 Tobias Platenupdate testcase for ldst
2021-06-06 Cesar StraussStart a new self-contained test suite for LDSTCompUnit
2021-06-01 Tobias Platentest_ldst_pi.py: add new test case
2021-05-29 Tobias Platentest_ldst_pi.py: first version of test_dcache_random()
2021-05-29 Tobias Platentest_ldst_pi.py: more test_dcache_regression()
2021-05-26 Luke Kenneth Casso... add ldst PortInterface misalign unit test (underway)
2021-05-25 Tobias Platentest_ldst_pi.py: fix race condition causing early stop
2021-05-15 Tobias Platentest_ldst_pi.py: add dcache regression and random test...
2021-05-14 Luke Kenneth Casso... add radix MMU "miss" test
2021-05-14 Luke Kenneth Casso... sort out LoadStore1 misalignment FSM, also required...
2021-05-14 Luke Kenneth Casso... add misaligned load through MMU (which is incorrectly...
2021-05-13 Luke Kenneth Casso... minor rework of wb_get, make generic
2021-05-13 Luke Kenneth Casso... added STORE test in test_ldst_pi.py, and it worked...
2021-05-13 Luke Kenneth Casso... fix wb_get error where data was being corrupted
2021-05-13 Luke Kenneth Casso... add read at different locations in test_ldst_pi.py
2021-05-13 Luke Kenneth Casso... add some data for MMU to actually look up
2021-05-13 Luke Kenneth Casso... putting in a lot more debug print statements in DCache...
2021-05-12 Luke Kenneth Casso... add dcache tlb / pte test
2021-05-12 Luke Kenneth Casso... move dcache unit test to separate test_dcache.py
2021-05-12 Luke Kenneth Casso... experimentation with MMU-enabled LoadStore1 through...
2021-05-12 Luke Kenneth Casso... add debug info, update comments, disable dcache in...
2021-05-12 Luke Kenneth Casso... start doing virtual memory queries via PortInterface...
2021-05-12 Luke Kenneth Casso... whoops missing default zero (no idea how)
2021-05-12 Luke Kenneth Casso... addcomments for MMU PortInterface test (how it, um...
2021-05-12 Luke Kenneth Casso... bit of a hack to get test_mmu_dcache_pi.py operational.
2021-05-12 Luke Kenneth Casso... whitespace
2021-05-11 Luke Kenneth Casso... pass through MSR.PR through PortInterface, into LoadStore1
2021-05-09 Luke Kenneth Casso... add misalign flag to PortInterfaceBase
2021-05-01 Luke Kenneth Casso... whitespace
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-02-24 Tobias Platenwb_get: write outputs to seperate logfile too
2021-02-20 Luke Kenneth Casso... remove massive code-duplication, move simple "self...
2021-01-01 Cesar StraussAdd zero CR test case and fix comments
2021-01-01 Cesar StraussAdd test cases with rc=1
2021-01-01 Cesar StraussMake all ports the same size, on the test ALU
2021-01-01 Cesar StraussAdd CR output port to test cases
2021-01-01 Cesar StraussMove NOP test case earlier
2020-12-31 Cesar StraussImplement and test NOP in the test ALU
2020-12-31 Cesar StraussDon't use OP_NOP for zero-delay subtraction
2020-12-31 Cesar StraussTest first input port being masked out
2020-12-31 Cesar StraussTest masked-out second input port
2020-12-31 Cesar StraussShow rdmaskn and wrmask in GTKWave
2020-12-31 Cesar StraussUse the increment operator
2020-12-31 Cesar StraussAdd support for masked write operations
2020-12-31 Cesar StraussClarify reason for holding rdmaskn valid during the...
2020-12-31 Cesar StraussRemove previous version of the CompUnit parallel unit...
2020-12-31 Cesar StraussOnly hold the decoder signals for one cycle, along...
2020-12-30 Cesar StraussTest the rdmaskn control signal
2020-12-07 Cesar StraussDisplay the instruction type as a vector on cxxsim
2020-12-06 Cesar StraussUpdate GTKWave documents to work with latest cxxsim
2020-11-24 Cesar StraussFix some typos and whitespace
2020-11-24 Cesar StraussPort the DummyALU test case to the new parallel issuer
2020-11-23 Cesar StraussResults are now a list, so "expected" should follow...
2020-11-23 Cesar StraussParameterize the issuer on the number of operands and...
2020-11-22 Cesar StraussRefactor the ALU operation issuer into a class
2020-11-22 Cesar StraussPort the ALU test case to the new parallel test style
2020-11-22 Cesar StraussAdd a GTKWave document to the ALU test case
2020-11-19 Cesar StraussSeparate input and output ports by color
2020-11-19 Cesar StraussExplain the test cases
2020-11-18 Cesar StraussSeparate individual traces for each rel_o/go_i port
2020-11-16 Cesar StraussAdd a transaction counter to producers and consumers
2020-11-15 Cesar StraussImplement ResultConsumer and port the Shifter unit...
2020-11-14 Cesar StraussMove the DUT driver to within the test case process
2020-11-14 Cesar StraussFix and enable the regspec test for the Shifter
2020-10-28 Cesar StraussImplement an operand producer that talks the rel_o...
2020-10-18 Cole Poirieruse random.seed to generate repro cases of the two...
2020-10-08 Luke Kenneth Casso... minor icache cleanup
2020-10-08 Cole Poiriersecond attempt at https://bugs.libre-soc.org/show_bug...
2020-10-08 Cole Poirierremove singleton dict per https://bugs.libre-soc.org...
2020-10-08 Cole Poirierfirst attempt at 3) of
2020-10-08 Cole Poiriermodify wb_get per 1) of https://bugs.libre-soc.org...
2020-10-06 Tobias Platentest_mmu_dcache_pi.py
2020-10-01 Cesar StraussAdd GTKWave document to test_compunit_fsm
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