shrink test memory size down to only 64 words
[soc.git] / src / soc / experiment /
2020-06-26 Luke Kenneth Casso... shrink test memory size down to only 64 words
2020-06-26 Luke Kenneth Casso... code-morph which redirects lsmem unit test through...
2020-06-25 Luke Kenneth Casso... allow Pi2LSUI to accept incoming PortInterface and...
2020-06-25 Luke Kenneth Casso... add extra parameter, mask_wid, to TestMemLoadStoreUnit
2020-06-25 Luke Kenneth Casso... start connecting up Pi2LSUI
2020-06-25 Luke Kenneth Casso... add LenExpand module, tidyup on docstring
2020-06-25 Luke Kenneth Casso... add beginnings of Pi2LSUI
2020-06-25 Luke Kenneth Casso... add attempt at mapping between PortInterface and LoadSt...
2020-06-25 Luke Kenneth Casso... rename LoadStoreInterface signals to include _i and...
2020-06-25 Luke Kenneth Casso... whitespace
2020-06-24 Michael NolanRevert "modify PortInterface so subfields include the...
2020-06-24 Michael NolanHave lsmem handle stall and valid signals correctly
2020-06-24 Michael NolanAdd handling of byte reads and writes
2020-06-24 Michael NolanAdd more complete testbench for lsmem.py
2020-06-24 Michael NolanSuper basic first try of testmem with load store unit...
2020-06-24 Luke Kenneth Casso... import minerva and use LoadStoreUnitInterface
2020-06-24 Michael NolanAdd specification for load store interface
2020-06-23 Michael Nolanmodify PortInterface so subfields include the port...
2020-06-23 Luke Kenneth Casso... annoying error in latest nmigen
2020-06-22 Luke Kenneth Casso... remove unused module
2020-06-22 Luke Kenneth Casso... simplified L0CacheBuffer down to a "PortInterface Arbiter"
2020-06-22 Luke Kenneth Casso... add TestMemoryPortInterface class which is designed...
2020-06-22 Luke Kenneth Casso... comments for LDST CompUnit test
2020-06-22 Luke Kenneth Casso... enable byte-reverse in CompLDSTUnit test
2020-06-22 Luke Kenneth Casso... remove CompLDSTOpSubset, replace with just data_len.
2020-06-22 Luke Kenneth Casso... move BE/LE byte-reverse into LDSTCompUnit
2020-06-19 Luke Kenneth Casso... add TODO comments to upgrade L0CacheBuffer to a new...
2020-06-16 Luke Kenneth Casso... set up a TestIssuer class with a FSM for doing instruct...
2020-06-16 Luke Kenneth Casso... add ports to TestMemory
2020-06-14 Luke Kenneth Casso... add in byte-reverse from op PowerDecode2 field
2020-06-14 Luke Kenneth Casso... error in address width (truncated) in setting up L0Cach...
2020-06-14 Luke Kenneth Casso... error in naming that ended up in gtkwave from a proxy
2020-06-14 Luke Kenneth Casso... add byte-reversal on LD and ST in L0CacheBuffer
2020-06-13 Cesar StraussWait for all active rel signals to be high, and only...
2020-06-11 Luke Kenneth Casso... some ugly hacks that get LD/ST immediate working
2020-06-11 Luke Kenneth Casso... even more complexity in CompALUMulti, to deal with...
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Luke Kenneth Casso... rename unit test function in ld/st compalu_multi
2020-06-10 Luke Kenneth Casso... hmmm very confused about LD/ST CompUnit unit test
2020-06-10 Luke Kenneth Casso... wrong data structure being imported, duplicate CompLDST...
2020-06-10 Luke Kenneth Casso... remove old code
2020-06-10 Luke Kenneth Casso... set data_len in compldst_multi unit test
2020-06-10 Luke Kenneth Casso... yield ports from data_o and addr_o
2020-06-10 Luke Kenneth Casso... expand LenExpand to 4 bits in order to cover 1/2/4...
2020-06-10 Luke Kenneth Casso... got L0CacheBuffer shift/mask working on a preliminary...
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Luke Kenneth Casso... add use of classes in L0Cache unit tests
2020-06-10 Luke Kenneth Casso... start using unittest suite in l0_cache.py
2020-06-10 Luke Kenneth Casso... add in LenExpander to L0CacheBuffer, not used yet
2020-06-10 Tobias Platenmake resetless for all signals in DataMergerRecord
2020-06-09 Cesar StraussKeep the sequencer in the "done" state until ready_i...
2020-06-09 Luke Kenneth Casso... rename truncaddr to splitaddr, return LSBs and MSBs
2020-06-09 Luke Kenneth Casso... add len-expander to L0CacheBuffer, so as to be able...
2020-06-09 Tobias Platenundo code removed by commit 12297566322355ce5fed2e2a546...
2020-06-09 Tobias Platenelaborate function for DualPortSplitter
2020-06-09 Cesar StraussAvoid a combinatorial loop on valid_o
2020-06-09 Tobias Platenfixes for DualPortSplitter
2020-06-09 Luke Kenneth Casso... make DataMerger record reset_less
2020-06-09 Luke Kenneth Casso... add truncaddr function to L0CacheBuffer test class
2020-06-09 Luke Kenneth Casso... add convenience variables in TestMemory
2020-06-08 Luke Kenneth Casso... move datamerger proof into standard directory location...
2020-06-07 Cesar StraussAssign the one-clock delay operation from ADD to SHR
2020-06-07 Cesar StraussTry responding with ready_i on the same cycle as valid_o
2020-06-07 Cesar StraussAssert valid_o one clock early, as alu_done is asserted
2020-06-07 Cesar StraussMake the test ALU conform to the valid/ready protocol
2020-06-06 Luke Kenneth Casso... expand regwid to 64 in l0_cache test
2020-06-06 Luke Kenneth Casso... allow Mem initialisation in ISACaller
2020-06-06 Luke Kenneth Casso... write-mask made from LD and Update mode (for data_o...
2020-06-06 Luke Kenneth Casso... LDSTCompUnit test data structures linked up, starting...
2020-06-06 Luke Kenneth Casso... allow CompLDSTOpSubset to be passed through to LDSTCompUnit
2020-06-06 Luke Kenneth Casso... set up LDSTCompUnit using regspec
2020-06-06 Luke Kenneth Casso... add extra bugreport link
2020-06-06 Luke Kenneth Casso... whitespace
2020-06-06 Luke Kenneth Casso... whitespace indentation
2020-06-06 Luke Kenneth Casso... whoops dest%d_o not dest%d_i
2020-06-05 Tobias Platenfix proof_datamerger (see 216#c56)
2020-06-05 Luke Kenneth Casso... add comments and start of elaborate
2020-06-05 Tobias Platenimplement init function of DualPortSplitter
2020-06-05 Tobias Platenuncomment rtlil.convert in test_l0_cache that causes...
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-06-03 Tobias Platenmore work on proof_datamerger.py
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Tobias Platenwhitespace fix for proof_datamerger.py
2020-06-03 Cesar StraussCheck completion of the sub-processes
2020-06-03 Cesar StraussSimplify immediate check
2020-06-03 Cesar StraussPreliminary check of the alu protocol
2020-06-03 Cesar StraussPass along the operand, in the cycle in which go is...
2020-06-02 Luke Kenneth Casso... argh - bad hack, detecting when there are no registers...
2020-06-02 Tobias Platenproof_datamerger: proof that output is zero when idle
2020-06-02 Cesar StraussAllow at least one operand to be fetched
2020-06-02 Cesar StraussHold rdmaskn active during the busy_o cycle
2020-06-01 Luke Kenneth Casso... sigh - another instance where write-mask needed to...
2020-06-01 Tobias Platenproof_datamerger wip
2020-06-01 Cesar StraussAdd rdmaskn parameter and assert it along issue_i
2020-05-31 Luke Kenneth Casso... add comments for MultiCompUnit parallel test
2020-05-31 Luke Kenneth Casso... remove unneeded imports
2020-05-31 Luke Kenneth Casso... split out compalu unit tests to separate module (gettin...
2020-05-31 Luke Kenneth Casso... HA! found a bug in MultiCompUnit handling of write...
2020-05-30 Luke Kenneth Casso... add in use of "Settle"
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