update TestRunner, SVSTATE is now a class that inherits from SelectableInt
[soc.git] / src / soc / experiment /
2021-07-14 Tobias Platenadd more debug outputs, pass dcbz to loadstore/dcache
2021-07-14 Tobias Platendcache: improve debug output
2021-07-11 Tobias Platenmore work on test_dcbz_pi.py
2021-07-11 Tobias Platenimplement pi_dcbz
2021-07-11 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-07-11 Tobias Platenadd test_dcbz_pi.py (skeleton only)
2021-07-10 Cesar StraussAdd new traces to the GTKWave document
2021-07-10 Cesar StraussAdd operand producers to the parallel LDST Compunit...
2021-07-10 Cesar StraussDetect unexpected operand fetches and produced results
2021-07-07 Cesar StraussStart of a GTKWave document for the LDST CompUnit paral...
2021-07-04 Cesar StraussBeginning of a class to make a parallel test case for...
2021-06-30 Tobias Platencut down on time by uncommenting data not needed, addin...
2021-06-28 Tobias Platenupdate ldst test case by adding precise timing
2021-06-20 Tobias Platendcache: add debug output
2021-06-20 Tobias Platenupdate test_ldst_pi.py
2021-06-18 Tobias Platenuncomment test_dcache_random
2021-06-14 Tobias Platenupdate testcase for ldst
2021-06-06 Cesar StraussStart a new self-contained test suite for LDSTCompUnit
2021-06-01 Tobias Platentest_ldst_pi.py: add new test case
2021-05-29 Tobias Platentest_ldst_pi.py: first version of test_dcache_random()
2021-05-29 Tobias Platentest_ldst_pi.py: more test_dcache_regression()
2021-05-26 Luke Kenneth Casso... add ldst PortInterface misalign unit test (underway)
2021-05-25 Tobias Platentest_ldst_pi.py: fix race condition causing early stop
2021-05-15 Tobias Platentest_ldst_pi.py: add dcache regression and random test...
2021-05-14 Luke Kenneth Casso... add radix MMU "miss" test
2021-05-14 Luke Kenneth Casso... sort out LoadStore1 misalignment FSM, also required...
2021-05-14 Luke Kenneth Casso... add misaligned load through MMU (which is incorrectly...
2021-05-13 Luke Kenneth Casso... minor rework of wb_get, make generic
2021-05-13 Luke Kenneth Casso... added STORE test in test_ldst_pi.py, and it worked...
2021-05-13 Luke Kenneth Casso... yet more debug log stuff for DCache, this time on Cache...
2021-05-13 Luke Kenneth Casso... fix wb_get error where data was being corrupted
2021-05-13 Luke Kenneth Casso... add read at different locations in test_ldst_pi.py
2021-05-13 Luke Kenneth Casso... add some data for MMU to actually look up
2021-05-13 Luke Kenneth Casso... ha, hilarious: swapped TLBUpdate output sizes db_out...
2021-05-13 Luke Kenneth Casso... whoops TLBIE must *clear* the valid bit not set it...
2021-05-13 Luke Kenneth Casso... more debug Display in dcache.py
2021-05-13 Luke Kenneth Casso... putting in a lot more debug print statements in DCache...
2021-05-12 Luke Kenneth Casso... add dcache tlb / pte test
2021-05-12 Luke Kenneth Casso... move dcache unit test to separate test_dcache.py
2021-05-12 Luke Kenneth Casso... experimentation with MMU-enabled LoadStore1 through...
2021-05-12 Luke Kenneth Casso... add debug info, update comments, disable dcache in...
2021-05-12 Luke Kenneth Casso... start doing virtual memory queries via PortInterface...
2021-05-12 Luke Kenneth Casso... whoops missing default zero (no idea how)
2021-05-12 Luke Kenneth Casso... addcomments for MMU PortInterface test (how it, um...
2021-05-12 Luke Kenneth Casso... bit of a hack to get test_mmu_dcache_pi.py operational.
2021-05-12 Luke Kenneth Casso... whitespace
2021-05-12 Luke Kenneth Casso... no need for sel0
2021-05-11 Luke Kenneth Casso... pass through MSR.PR through PortInterface, into LoadStore1
2021-05-11 Luke Kenneth Casso... connect MSR.PR to PortInterface in LDSTCompUnit
2021-05-11 Luke Kenneth Casso... add msr_pr bit in PortInterface
2021-05-10 Luke Kenneth Casso... whoops, indentation issue on m.If/m.Else in dcache.py
2021-05-10 Luke Kenneth Casso... add links to set associative image, and bugreport
2021-05-09 Luke Kenneth Casso... update code-comments
2021-05-09 Luke Kenneth Casso... add misalign flag to PortInterfaceBase
2021-05-04 Luke Kenneth Casso... more rename of exception_o to exc_o, add convenience...
2021-05-04 Luke Kenneth Casso... wire in exc_o.happened into write-cancellation of LDSTC...
2021-05-04 Luke Kenneth Casso... comments, and change name of LDSTCompUnit exception_o...
2021-05-04 Luke Kenneth Casso... code-comments for LDSTCompUnit
2021-05-02 Luke Kenneth Casso... add nc argument to dcache load/store tests
2021-05-02 Luke Kenneth Casso... quick hack to SRAM test and to dcache to enable classic...
2021-05-01 Luke Kenneth Casso... dcache store test: data goes in one cycle AFTER valid...
2021-05-01 Cesar StraussAdd GTKWave documents to each DCache unit test
2021-05-01 Luke Kenneth Casso... whitespace
2021-05-01 Luke Kenneth Casso... missing self.
2021-05-01 Luke Kenneth Casso... resolve DriverConflict in TstL0CacheBuffer, really...
2021-04-26 Luke Kenneth Casso... simple regression dcache test was faulty. wishbone...
2021-04-26 Luke Kenneth Casso... incorrect indentation in dcache rams
2021-04-26 Luke Kenneth Casso... simplify dcache test
2021-04-25 Luke Kenneth Casso... spelling mistake
2021-04-25 Luke Kenneth Casso... remove RegStage1.real_adr temporary from dcache
2021-04-25 Luke Kenneth Casso... do not overwrite parameter ra in dcache
2021-04-25 Luke Kenneth Casso... comment out dcache_store from test, not the problem
2021-04-25 Luke Kenneth Casso... remove unneeded code
2021-04-25 Luke Kenneth Casso... read req in wb_in.stall, dcache
2021-04-25 Luke Kenneth Casso... add single regression test for dcache
2021-04-25 Luke Kenneth Casso... add TODO comment in dcache
2021-04-25 Luke Kenneth Casso... move Signals in dcache to relevant context
2021-04-25 Luke Kenneth Casso... dcache Elif used where If should have been
2021-04-25 Luke Kenneth Casso... whoops should be cyc & ~ack
2021-04-25 Luke Kenneth Casso... hard-code dcache stall signal to non-pipelined mode
2021-04-24 Luke Kenneth Casso... increase memory size in dcache test
2021-04-24 Luke Kenneth Casso... increase size of random dcache testing by 10
2021-04-24 Luke Kenneth Casso... fix errors in dcache unit test
2021-04-23 Luke Kenneth Casso... move over to from openpower imports
2021-04-23 Luke Kenneth Casso... removing more as moved over to openpower-isa
2021-04-22 Luke Kenneth Casso... add debugging and buffering to CacheRam
2021-04-22 Luke Kenneth Casso... whitespace
2021-04-22 Luke Kenneth Casso... r1.end_row_ix off-by-one in dcache
2021-04-22 Luke Kenneth Casso... sync missing in dcache
2021-04-22 Luke Kenneth Casso... dcache.py code-comments
2021-04-22 Luke Kenneth Casso... cleanup dcache
2021-04-22 Luke Kenneth Casso... error using sync, should have been comb
2021-04-21 Luke Kenneth Casso... experimenting with dcache
2021-04-20 Luke Kenneth Casso... use soc.bus.sram instead of nmigen_soc.wishbone.sram
2021-04-06 Tobias Platenadd mmu_states.dia
2021-02-24 Tobias Platenwb_get: write outputs to seperate logfile too
2021-02-20 Luke Kenneth Casso... remove massive code-duplication, move simple "self...
2021-02-16 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-02-15 Cole Poirierremove file experiment/formal/proof_icache.py as it...
2021-02-09 colepoirieradd missing newline at end of experiment/formal/.gitignore
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