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rename InternalOp to MicrOp
[soc.git]
/
src
/
soc
/
fu
/
common_output_stage.py
2020-07-12
Luke Kenneth Casso...
rename InternalOp to MicrOp
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2020-07-09
Luke Kenneth Casso...
add regression test for div overflow case
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2020-07-09
Luke Kenneth Casso...
slightly different so handling in common output stage
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2020-07-09
Luke Kenneth Casso...
bug #424 - 32/64 bit is a *global* flag not a per-op one
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2020-07-09
Luke Kenneth Casso...
test top bit 31 in 32-bit mode for CR0 creation
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2020-07-09
Luke Kenneth Casso...
create new DivMulOutputData which does not have CA...
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2020-07-09
Luke Kenneth Casso...
make carry output handling optional in common output...
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2020-07-08
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-07-05
Luke Kenneth Casso...
big reorg on PowerDecoder2, actually Decode2Execute1Type
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2020-06-06
Luke Kenneth Casso...
comments / whitespace
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2020-06-01
Luke Kenneth Casso...
remove zero/invert from ShiftRot Input Record
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2020-06-01
Luke Kenneth Casso...
minor adjustment, zero test in ALU output stage
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2020-05-31
Luke Kenneth Casso...
copy in cr0.data into cr0 temp, not whole of cr0 (inclu...
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2020-05-31
Luke Kenneth Casso...
write cr0 when op.write_cr.ok is set
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2020-05-30
Luke Kenneth Casso...
set CR0 output when OP_CMP or OP_CMPEQB need it
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2020-05-28
Luke Kenneth Casso...
update comment
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2020-05-24
Luke Kenneth Casso...
start using Data in pipelines
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2020-05-22
Luke Kenneth Casso...
split out Logical Input and Output stages to common...
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