Convert a few more tests to be able to use cxxsim
[soc.git] / src / soc / fu / compunits / test /
2020-06-03 Luke Kenneth Casso... move over to using power_regspec_map.py from PowerDecod...
2020-06-03 Luke Kenneth Casso... move obtaining simulator data into common function...
2020-06-02 Luke Kenneth Casso... argh - bad hack, detecting when there are no registers...
2020-06-02 Luke Kenneth Casso... take out unneeded code, add Settle() to see if it helps...
2020-06-02 Luke Kenneth Casso... hooray, get_cu_inputs now common to both types of tests
2020-06-02 Luke Kenneth Casso... remove unneeded variable
2020-06-02 Luke Kenneth Casso... decode fast spr for OP_BCREG CTR, TAR and LR
2020-06-02 Luke Kenneth Casso... debugging branch fast registers
2020-06-02 Luke Kenneth Casso... add read-write register numbering detection
2020-06-02 Luke Kenneth Casso... whitespace
2020-06-02 Luke Kenneth Casso... rename regspecs to give a consistent naming scheme
2020-06-01 Luke Kenneth Casso... remove reading port 3 for CR pipeline. RS moved to...
2020-06-01 Luke Kenneth Casso... okaaay add a "rdflags" function which obtains the yes...
2020-06-01 Luke Kenneth Casso... RS moved to port 1 (from port 3), remove need in ALU...
2020-06-01 Luke Kenneth Casso... argh - need to zero the src_i input after "Read" is...
2020-06-01 Luke Kenneth Casso... remove xer so/ov, swap rs/rb to correct(?) order in...
2020-06-01 Luke Kenneth Casso... add first version of ShiftRot CompUnit test
2020-06-01 Luke Kenneth Casso... add assertions for branch compunit output
2020-06-01 Luke Kenneth Casso... decode SPRs for branch
2020-06-01 Luke Kenneth Casso... add first version compunit branch test
2020-06-01 Luke Kenneth Casso... whoops need to read RS in CR inputs test
2020-06-01 Luke Kenneth Casso... add first version of CR CompUnit test
2020-05-31 Luke Kenneth Casso... bit-test on the function-unit value being tested
2020-05-31 Luke Kenneth Casso... add logical compunit test
2020-05-31 Luke Kenneth Casso... comment inputs and outputs from ALU unit test
2020-05-31 Luke Kenneth Casso... imports - use of globals. baaaad
2020-05-31 Luke Kenneth Casso... remove unneeded code and inputs. convert to "naming...
2020-05-31 Luke Kenneth Casso... split out common code from test_alu_compunit.py
2020-05-31 Luke Kenneth Casso... de-hard-code-ify getting results from MultiCompUnit
2020-05-31 Luke Kenneth Casso... OP_CMP is requesting a change of the output register...
2020-05-31 Luke Kenneth Casso... more debug statements
2020-05-31 Luke Kenneth Casso... add in more CR debug statements
2020-05-31 Luke Kenneth Casso... write cr0 when op.write_cr.ok is set
2020-05-31 Luke Kenneth Casso... comment out xer ov/so for now
2020-05-30 Luke Kenneth Casso... get carry from cr write_cr
2020-05-30 Luke Kenneth Casso... add in write-mask into MultiCompUnit and MCU-ALU unit...
2020-05-30 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-30 Luke Kenneth Casso... create read-mask for ALU CompUnit: switches off optiona...
2020-05-30 Luke Kenneth Casso... mess - but a functional mess. ALU-MultiCompUnit semi...
2020-05-30 Luke Kenneth Casso... grab other results from ALU pipeline in compunit test
2020-05-30 Luke Kenneth Casso... order of XER so/ca wrong way round from regspec
2020-05-29 Luke Kenneth Casso... trigger read ALU ready/valid from latch as well
2020-05-28 Luke Kenneth Casso... extra check on rd.req in test_alu_compunit
2020-05-28 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-28 Luke Kenneth Casso... debug-print rd/wr rel in test_alu_compunit
2020-05-28 Luke Kenneth Casso... debugging test_alu_compunit.py
2020-05-28 Luke Kenneth Casso... start on a compunit ALU test