Convert a few more tests to be able to use cxxsim
[soc.git] / src / soc / fu / compunits / test /
2020-09-26 Cesar StraussConvert a few more tests to be able to use cxxsim
2020-09-02 Luke Kenneth Casso... series of extensive modifications to fix long-standing...
2020-08-29 Luke Kenneth Casso... CR FXM becomes a full mask.
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... sorting out shift_rot to use new output stage data...
2020-08-14 Luke Kenneth Casso... fix test_compunit.py after moving decoder rdflags function
2020-08-14 Luke Kenneth Casso... sort out instruction stop/cancel when adding a new...
2020-08-04 Luke Kenneth Casso... msr and pc moved to "state" in PowerDecode2
2020-07-31 Luke Kenneth Casso... missed go_i/rel_o rename
2020-07-29 Luke Kenneth Casso... bit of a big change: add prefixes "cu_" to all CompUnit...
2020-07-29 Jacob Lifshayadd __init__.py to all source directories
2020-07-26 Luke Kenneth Casso... argh add yet another latch to detect when LD/ST has...
2020-07-26 Luke Kenneth Casso... sigh, issue with detection/waiting for LD/ST CompUnit
2020-07-26 Luke Kenneth Casso... convert LDST test to accumulator style
2020-07-26 Luke Kenneth Casso... convert Branch test to accumulator style
2020-07-26 Luke Kenneth Casso... convert SPR test to accumulator style
2020-07-26 Luke Kenneth Casso... convert TRAP test to accumulator style
2020-07-26 Luke Kenneth Casso... convert CR test to accumulator style
2020-07-26 Luke Kenneth Casso... convert shift_rot test to new base accumulator style
2020-07-26 Luke Kenneth Casso... convert logical test case to new base class accumulator...
2020-07-26 Luke Kenneth Casso... convert ALU to new accumulator style
2020-07-26 Luke Kenneth Casso... run subtest, indentation getting too large, move to...
2020-07-26 Luke Kenneth Casso... get div compunit test running (use new way to accumulat...
2020-07-25 Luke Kenneth Casso... add div compunit test
2020-07-25 Luke Kenneth Casso... wait until pipeline indicates that its output is valid...
2020-07-25 Luke Kenneth Casso... move reset of rdmaskn to after "busy"
2020-07-22 Jacob LifshayMerge remote-tracking branch 'origin/master'
2020-07-22 Jacob Lifshayformat code
2020-07-21 Luke Kenneth Casso... interesting bug in test_compunit.py when there are...
2020-07-21 Luke Kenneth Casso... move cia and msr to trap input record
2020-07-16 Luke Kenneth Casso... get shiftrot compunit working
2020-07-16 Luke Kenneth Casso... get branch compunit working (missing bigendian arg)
2020-07-16 Luke Kenneth Casso... get trap compunit test working, adding bigendian and msr
2020-07-11 Luke Kenneth Casso... add bigendian flag
2020-07-11 Luke Kenneth Casso... add endian
2020-07-11 Luke Kenneth Casso... sorting out bigendian/littleendian including in qemu
2020-07-10 Luke Kenneth Casso... re-add rc/oe back into LDST input record
2020-07-10 Luke Kenneth Casso... whew panic over, missed a bigendian argument in test_co...
2020-07-08 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-07-06 Luke Kenneth Casso... adding mtspr tests
2020-07-06 Luke Kenneth Casso... sort out initialisation of TstL0CacheBuffer in ldst...
2020-07-05 Luke Kenneth Casso... check trap compunit output properly
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth Casso... sigh read and write xer detection, fix spr and trap...
2020-07-05 Luke Kenneth Casso... check spr1 in test spr compunit
2020-07-05 Luke Kenneth Casso... add first spr compunit test (not working yet)
2020-07-04 Luke Kenneth Casso... more updating spr1/spr2 to fast1/fast2
2020-07-04 Luke Kenneth Casso... oops initialise Function Unit class with idx
2020-07-04 Luke Kenneth Casso... add first cookie-cut test_trap_compunit.py
2020-06-28 Luke Kenneth Casso... got Pi2LSUI FSM working
2020-06-27 Luke Kenneth Casso... make Memory accessible via TestSRAMBareLoadStoreUnit
2020-06-27 Luke Kenneth Casso... increase (double) address width in TstL0CacheBuffer
2020-06-22 Luke Kenneth Casso... simplified L0CacheBuffer down to a "PortInterface Arbiter"
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Luke Kenneth Casso... use while / exception in test_compunit loop
2020-06-17 Luke Kenneth Casso... decoding assembly instruction name, move to separate...
2020-06-17 Luke Kenneth Casso... get fu compunit test to use ISACaller instruction-memory
2020-06-17 Luke Kenneth Casso... start to add in independent execution into ISACaller
2020-06-17 Luke Kenneth Casso... use an independent power decoder in ISACaller
2020-06-15 Luke Kenneth Casso... move setup/check memory into helper functions for use...
2020-06-14 Luke Kenneth Casso... reasonably certain that the careful and slow use of...
2020-06-12 Luke Kenneth Casso... update ld/st test to see what is going on
2020-06-12 Luke Kenneth Casso... tracking down what looks like an error in the Simulator...
2020-06-12 Luke Kenneth Casso... debug printout of sim and hardware memory, shows mismat...
2020-06-12 Luke Kenneth Casso... use ALUHelpers in LDSTCompUnit test
2020-06-11 Luke Kenneth Casso... even more complexity in CompALUMulti, to deal with...
2020-06-11 Luke Kenneth Casso... fixing get_rd_sim_xer_ca, has to only read carry if...
2020-06-11 Luke Kenneth Casso... yield needed for unit tests to work (has to go)
2020-06-11 Luke Kenneth Casso... rename get_sim_cr_a to get_wr_sim_cr_a for now
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Luke Kenneth Casso... link ST.go directly to ST.rel
2020-06-10 Luke Kenneth Casso... re-do cookie-cut of alu test_pipe_caller.py over to...
2020-06-10 Luke Kenneth Casso... use ALUHelpers in output phase of test_alu_compunit.py
2020-06-07 Luke Kenneth Casso... add missing arg to ISA in test_compunit
2020-06-06 Luke Kenneth Casso... experimenting with setting up and testing memory
2020-06-06 Luke Kenneth Casso... work out how to initialise memory directly
2020-06-06 Luke Kenneth Casso... initialise L0 Memory from simulator memory
2020-06-06 Luke Kenneth Casso... wait a little for wr.rel to activate if wrmask is active
2020-06-06 Luke Kenneth Casso... allow Mem initialisation in ISACaller
2020-06-06 Luke Kenneth Casso... allow Mem in Simulator to be initialised
2020-06-06 Luke Kenneth Casso... use name of unit to write simulator/vcd file
2020-06-06 Luke Kenneth Casso... LDSTCompUnit test data structures linked up, starting...
2020-06-06 Luke Kenneth Casso... add special-case LDSTFunctionUnit
2020-06-06 Luke Kenneth Casso... add beginnings of LDST compunit test
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... no global variables in test suites
2020-06-04 Luke Kenneth Casso... remove unneeded imports
2020-06-04 Luke Kenneth Casso... use copy of FHDLTestCase
2020-06-04 Luke Kenneth Casso... connect up write-ports from Regfiles to FUs
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... use common get_cu_inputs for CR unit tests
2020-06-03 Luke Kenneth Casso... convert shift_rot tests to use common get_cu_inputs...
2020-06-03 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-03 Luke Kenneth Casso... reorganise ALU tests, move get_cu_inputs function to...
2020-06-03 Luke Kenneth Casso... worked out how to dynamically enable carry-in to ALU...
2020-06-03 Luke Kenneth Casso... correct overflow-enable flags for rdmask specs in ALU
2020-06-03 Luke Kenneth Casso... attempt to make carry-in and overflow-enable optional...
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