2021-05-09 |
Luke Kenneth Casso... | add MMU bugtracker link |
tree | commitdiff |
2021-05-09 |
Luke Kenneth Casso... | preference is to create a temp variable for comb and... |
tree | commitdiff |
2021-05-08 |
Luke Kenneth Casso... | add bugreport link to mmu |
tree | commitdiff |
2021-05-07 |
Tobias Platen | fix 'sync' referenced before assignment in src/soc... |
tree | commitdiff |
2021-05-07 |
Luke Kenneth Casso... | update comments and docstrings |
tree | commitdiff |
2021-05-07 |
Luke Kenneth Casso... | whoops, import error |
tree | commitdiff |
2021-05-07 |
Luke Kenneth Casso... | move LoadStore1 class to soc.fu.ldst.loadstore |
tree | commitdiff |
2021-05-07 |
Luke Kenneth Casso... | move dsisr and dar into LoadStore1 |
tree | commitdiff |
2021-05-05 |
Tobias Platen | fix bug in mmu/fsm.py |
tree | commitdiff |
2021-05-04 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-05-04 |
Tobias Platen | implement MFSPR the same way as fu/spr/main_stage.py |
tree | commitdiff |
2021-05-04 |
Tobias Platen | upate dsisr and dar using sync |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | more rename of exception_o to exc_o, add convenience... |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | rename IntegerData to FUBaseData |
tree | commitdiff |
2021-05-04 |
Luke Kenneth Casso... | comment out nc (nocache), it seems to actually work |
tree | commitdiff |
2021-05-03 |
Luke Kenneth Casso... | MMU: get store to activate only when data is available... |
tree | commitdiff |
2021-05-03 |
Luke Kenneth Casso... | disable the cache for now, whilst testing read/write... |
tree | commitdiff |
2021-05-02 |
Luke Kenneth Casso... | use Const to define bit-length when comparing top nibbl... |
tree | commitdiff |
2021-05-02 |
Luke Kenneth Casso... | mmu FSM store in dcache: only put data onto d_in on... |
tree | commitdiff |
2021-05-02 |
Luke Kenneth Casso... | return d_out.valid instead of always "ok" in MMU FSM |
tree | commitdiff |
2021-05-02 |
Luke Kenneth Casso... | HACK WARNING: disable d-cache on hard-coded address... |
tree | commitdiff |
2021-05-01 |
Luke Kenneth Casso... | store data in microwatt dcache goes in one cycle AFTER... |
tree | commitdiff |
2021-05-01 |
Luke Kenneth Casso... | only do dcache lookup for now |
tree | commitdiff |
2021-04-30 |
Luke Kenneth Casso... | debug and stop on mmu test_pipe_caller.py |
tree | commitdiff |
2021-04-30 |
Luke Kenneth Casso... | comments on dcache-to-mmu link |
tree | commitdiff |
2021-04-30 |
Luke Kenneth Casso... | add a TestSRAM variant of LoadStore1, for being able... |
tree | commitdiff |
2021-04-30 |
Luke Kenneth Casso... | hook up dcache wb_in/out to PortInterfaceBase Wishbone... |
tree | commitdiff |
2021-04-30 |
Luke Kenneth Casso... | set up LoadStore1 in ConfigMemoryPortInterface and... |
tree | commitdiff |
2021-04-29 |
Luke Kenneth Casso... | comment out adding mmu and dcache to pspec in MMU FSM |
tree | commitdiff |
2021-04-29 |
Luke Kenneth Casso... | move dcache into Loadstore1 |
tree | commitdiff |
2021-04-27 |
Luke Kenneth Casso... | return read data out from Loadstore1 only when valid |
tree | commitdiff |
2021-04-26 |
Luke Kenneth Casso... | hook up MSR into MMU (TODO, use a lot less bits) |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move MMU Testcase to openpower.test |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | import from openpower.endian |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | use openpower.test.common |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | more openpower-isa conversion |
tree | commitdiff |
2021-04-23 |
Luke Kenneth Casso... | move over to from openpower imports |
tree | commitdiff |
2021-04-20 |
Luke Kenneth Casso... | cannot pass in arguments to Core - must be done with... |
tree | commitdiff |
2021-03-30 |
Alain D D Williams | Merge branch 'master' of git.libre-soc.org:soc |
tree | commitdiff |
2021-03-28 |
Luke Kenneth Casso... | rather invasive reduction of SPR regfile size |
tree | commitdiff |
2021-03-02 |
Luke Kenneth Casso... | comment out changing SPR 720 because 720 is not support... |
tree | commitdiff |
2021-03-02 |
Luke Kenneth Casso... | sort out SPR setting in MMU |
tree | commitdiff |
2021-03-02 |
Luke Kenneth Casso... | operating correctly, not directing MMU SPRs to SPR... |
tree | commitdiff |
2021-03-02 |
Luke Kenneth Casso... | must always set ok for writing out data otherwise it... |
tree | commitdiff |
2021-02-24 |
Tobias Platen | update mmu testcase |
tree | commitdiff |
2021-02-20 |
Luke Kenneth Casso... | correct arguments, set microwatt_mmu=True, pass in... |
tree | commitdiff |
2021-02-20 |
Luke Kenneth Casso... | minor whitespace cleanup |
tree | commitdiff |
2021-02-20 |
Tobias Platen | mmu testcase: set MMU SPRs |
tree | commitdiff |
2021-02-20 |
Tobias Platen | add rom debugger |
tree | commitdiff |
2021-02-20 |
Tobias Platen | add mmu rom testcase |
tree | commitdiff |
2021-02-18 |
Tobias Platen | mmu: remove TestMemory |
tree | commitdiff |
2021-02-16 |
Tobias Platen | mmureq handling |
tree | commitdiff |
2021-02-16 |
Tobias Platen | dcache error handling |
tree | commitdiff |
2021-02-16 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2021-02-15 |
Tobias Platen | test case for MMU SPRs: PID and PRTBL |
tree | commitdiff |
2021-02-05 |
Tobias Platen | fix hanging simulation |
tree | commitdiff |
2021-02-04 |
Tobias Platen | src/soc/fu/mmu/fsm.py: add debug outputs for gtkwave |
tree | commitdiff |
2021-02-04 |
Tobias Platen | update test_issuer_mmu_data_path.py to handle SPRs |
tree | commitdiff |
2021-01-19 |
Tobias Platen | test_issuer_mmu_data_path.py: test both ld and st instr... |
tree | commitdiff |
2021-01-19 |
Tobias Platen | connect LDSTException to MMU and DCache |
tree | commitdiff |
2021-01-19 |
Tobias Platen | connect wishbone bus to test memory |
tree | commitdiff |
2021-01-18 |
Tobias Platen | fu/mmu/fsm.py: connect valid and load signals |
tree | commitdiff |
2021-01-17 |
Tobias Platen | add test memory for simulation |
tree | commitdiff |
2021-01-17 |
Tobias Platen | cleanup test_issuer_mmu_data_path.py |
tree | commitdiff |
2021-01-16 |
Tobias Platen | clean up test case for tlbie and dcbz |
tree | commitdiff |
2021-01-16 |
Tobias Platen | move microwatt_mmu bool variable to pspec |
tree | commitdiff |
2021-01-16 |
Tobias Platen | add new unittest: test_issuer_mmu_data_path.py |
tree | commitdiff |
2021-01-15 |
Tobias Platen | cleanup test_non_production_core.py |
tree | commitdiff |
2021-01-15 |
Tobias Platen | test_non_production_core.py: fix hanging test |
tree | commitdiff |
2021-01-15 |
Tobias Platen | test_non_production_core.py: wire instruction decoder... |
tree | commitdiff |
2021-01-14 |
Tobias Platen | add test case for mmu+NonProductionCore |
tree | commitdiff |
2021-01-07 |
Tobias Platen | set initial_sprs, cleanup mfspr testprog |
tree | commitdiff |
2021-01-07 |
Tobias Platen | mfspr is RT, SPR |
tree | commitdiff |
2021-01-06 |
Tobias Platen | first testcase for mmu: case_mfspr_after_invalid_load |
tree | commitdiff |
2021-01-06 |
Tobias Platen | fu/mmu/fsm.py: mfspr!=mtspr |
tree | commitdiff |
2020-11-17 |
Tobias Platen | testcase for dcbz |
tree | commitdiff |
2020-11-16 |
Tobias Platen | add class LoadStore1(PortInterfaceBase) |
tree | commitdiff |
2020-11-11 |
Tobias Platen | dcbz and tlbie first test, still incomplete |
tree | commitdiff |
2020-11-11 |
Tobias Platen | fu/mmu/test/test_pipe_caller.py test case for mfspr |
tree | commitdiff |
2020-11-08 |
Tobias Platen | mmu fsm testcase: add check_fsm_outputs based on functi... |
tree | commitdiff |
2020-11-08 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-11-08 |
Tobias Platen | mmu/fsm: test case for mtspr |
tree | commitdiff |
2020-11-07 |
Tobias Platen | fixed a bug in src/soc/fu/mmu/fsm.py |
tree | commitdiff |
2020-11-04 |
Tobias Platen | MMU: begin test case for 'dcbz' |
tree | commitdiff |
2020-11-03 |
Tobias Platen | fix broken unittest after installing power-instruction... |
tree | commitdiff |
2020-10-20 |
Tobias Platen | s/alu/fsm/g |
tree | commitdiff |
2020-10-20 |
Tobias Platen | test case for FSMMMUStage |
tree | commitdiff |
2020-10-08 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
tree | commitdiff |
2020-10-08 |
Tobias Platen | add WIP test_pipe_caller.py for mmu |
tree | commitdiff |
2020-10-08 |
Luke Kenneth Casso... | add incoming PortInterface to be connected to LoadStore... |
tree | commitdiff |
2020-09-21 |
Luke Kenneth Casso... | add missing file |
tree | commitdiff |
2020-09-15 |
Luke Kenneth Casso... | instantiate MMU from AllFunctionUnits |
tree | commitdiff |
2020-09-15 |
Luke Kenneth Casso... | do not need FAST regs in MMU |
tree | commitdiff |
2020-09-15 |
Luke Kenneth Casso... | add edge-triggering to dcache/mmu "valid" |
tree | commitdiff |
2020-09-15 |
Luke Kenneth Casso... | add OP_MFSPR to mmu |
tree | commitdiff |
2020-09-15 |
Luke Kenneth Casso... | use convenience vars |
tree | commitdiff |
2020-09-15 |
Luke Kenneth Casso... | add OP_TLBIE to mmu fsm |
tree | commitdiff |
2020-09-15 |
Luke Kenneth Casso... | add OP_DCBZ to mmu fsm, needs RA to be added to MMU... |
tree | commitdiff |
2020-09-15 |
Luke Kenneth Casso... | add MMU MTSPR connection into FSM |
tree | commitdiff |
2020-09-15 |
Luke Kenneth Casso... | add in MMU and DCache into MMU FSM |
tree | commitdiff |
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