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add LoadStore State enum
[soc.git] / src / soc / fu /
2021-05-08 Luke Kenneth Casso... add LoadStore State enum tree | commitdiff
2021-05-08 Luke Kenneth Casso... add bugreport link to mmu tree | commitdiff
2021-05-07 Tobias Platenfix 'sync' referenced before assignment in src/soc... tree | commitdiff
2021-05-07 Luke Kenneth Casso... start setting DSISR bits but commented out tree | commitdiff
2021-05-07 Luke Kenneth Casso... update comments and docstrings tree | commitdiff
2021-05-07 Luke Kenneth Casso... whoops, import error tree | commitdiff
2021-05-07 Luke Kenneth Casso... move LoadStore1 class to soc.fu.ldst.loadstore tree | commitdiff
2021-05-07 Luke Kenneth Casso... whoops was still copying output over in CommonOutputStage tree | commitdiff
2021-05-07 Luke Kenneth Casso... move dsisr and dar into LoadStore1 tree | commitdiff
2021-05-07 Luke Kenneth Casso... move zero-dest-pred in Common Output Stage to not copy... tree | commitdiff
2021-05-06 Luke Kenneth Casso... if zeroing is set, put zero into input or output as... tree | commitdiff
2021-05-05 Tobias Platenfix bug in mmu/fsm.py tree | commitdiff
2021-05-05 Luke Kenneth Casso... put sv_input_record_layout onto CompOpSubsetBase after all tree | commitdiff
2021-05-05 Luke Kenneth Casso... add SVP64 RM fields to ALU input record tree | commitdiff
2021-05-04 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... tree | commitdiff
2021-05-04 Tobias Platenimplement MFSPR the same way as fu/spr/main_stage.py tree | commitdiff
2021-05-04 Luke Kenneth Casso... add SVSTATE (SVSRR0) to TRAP pipeline tree | commitdiff
2021-05-04 Tobias Platenupate dsisr and dar using sync tree | commitdiff
2021-05-04 Luke Kenneth Casso... adding fast3 SPR to Trap pipeline and unit test tree | commitdiff
2021-05-04 Luke Kenneth Casso... add printout showing exception output from FUs tree | commitdiff
2021-05-04 Luke Kenneth Casso... more rename of exception_o to exc_o, add convenience... tree | commitdiff
2021-05-04 Luke Kenneth Casso... comments, and change name of LDSTCompUnit exception_o... tree | commitdiff
2021-05-04 Luke Kenneth Casso... remove exception from data on FUBaseData, explicitly... tree | commitdiff
2021-05-04 Luke Kenneth Casso... code-comments for LDSTCompUnit tree | commitdiff
2021-05-04 Luke Kenneth Casso... add LDSTException class to LDSTOutputData tree | commitdiff
2021-05-04 Luke Kenneth Casso... add option to add exception type to FUBaseData (pipe_data) tree | commitdiff
2021-05-04 Luke Kenneth Casso... rename IntegerData to FUBaseData tree | commitdiff
2021-05-04 Luke Kenneth Casso... comment out nc (nocache), it seems to actually work tree | commitdiff
2021-05-03 Luke Kenneth Casso... MMU: get store to activate only when data is available... tree | commitdiff
2021-05-03 Luke Kenneth Casso... disable the cache for now, whilst testing read/write... tree | commitdiff
2021-05-02 Luke Kenneth Casso... use Const to define bit-length when comparing top nibbl... tree | commitdiff
2021-05-02 Luke Kenneth Casso... mmu FSM store in dcache: only put data onto d_in on... tree | commitdiff
2021-05-02 Luke Kenneth Casso... return d_out.valid instead of always "ok" in MMU FSM tree | commitdiff
2021-05-02 Luke Kenneth Casso... HACK WARNING: disable d-cache on hard-coded address... tree | commitdiff
2021-05-01 Luke Kenneth Casso... store data in microwatt dcache goes in one cycle AFTER... tree | commitdiff
2021-05-01 Luke Kenneth Casso... only do dcache lookup for now tree | commitdiff
2021-04-30 Luke Kenneth Casso... debug and stop on mmu test_pipe_caller.py tree | commitdiff
2021-04-30 Luke Kenneth Casso... comments on dcache-to-mmu link tree | commitdiff
2021-04-30 Luke Kenneth Casso... add a TestSRAM variant of LoadStore1, for being able... tree | commitdiff
2021-04-30 Luke Kenneth Casso... hook up dcache wb_in/out to PortInterfaceBase Wishbone... tree | commitdiff
2021-04-30 Luke Kenneth Casso... set up LoadStore1 in ConfigMemoryPortInterface and... tree | commitdiff
2021-04-29 Luke Kenneth Casso... comment out adding mmu and dcache to pspec in MMU FSM tree | commitdiff
2021-04-29 Luke Kenneth Casso... move dcache into Loadstore1 tree | commitdiff
2021-04-27 Luke Kenneth Casso... return read data out from Loadstore1 only when valid tree | commitdiff
2021-04-26 Luke Kenneth Casso... hook up MSR into MMU (TODO, use a lot less bits) tree | commitdiff
2021-04-23 Luke Kenneth Casso... fix import error tree | commitdiff
2021-04-23 Luke Kenneth Casso... whitespace tree | commitdiff
2021-04-23 Luke Kenneth Casso... move logical tests to openpower.test tree | commitdiff
2021-04-23 Luke Kenneth Casso... add trap test cases tree | commitdiff
2021-04-23 Luke Kenneth Casso... move SPR tests to openpower.test tree | commitdiff
2021-04-23 Luke Kenneth Casso... move branch test cases to openpower.test tree | commitdiff
2021-04-23 Luke Kenneth Casso... move LDST tests to openpower.test tree | commitdiff
2021-04-23 Luke Kenneth Casso... move mul tests to openpower.test tree | commitdiff
2021-04-23 Luke Kenneth Casso... move div tests to openpower.test tree | commitdiff
2021-04-23 Luke Kenneth Casso... move div tests to openpower.test tree | commitdiff
2021-04-23 Luke Kenneth Casso... move ALU test cases to openpower.test tree | commitdiff
2021-04-23 Luke Kenneth Casso... move MMU Testcase to openpower.test tree | commitdiff
2021-04-23 Luke Kenneth Casso... move CR test cases to openpower.test tree | commitdiff
2021-04-23 Luke Kenneth Casso... move shiftrot test cases to openpower.test tree | commitdiff
2021-04-23 Luke Kenneth Casso... import from openpower.endian tree | commitdiff
2021-04-23 Luke Kenneth Casso... use openpower.test.common tree | commitdiff
2021-04-23 Luke Kenneth Casso... move more files to openpower-isa tree | commitdiff
2021-04-23 Luke Kenneth Casso... more openpower-isa conversion tree | commitdiff
2021-04-23 Luke Kenneth Casso... correct migration of openpower-isa tree | commitdiff
2021-04-23 Luke Kenneth Casso... more openpower import conversion tree | commitdiff
2021-04-23 Luke Kenneth Casso... move over to from openpower imports tree | commitdiff
2021-04-21 Cesar StraussAdd CR predication test case for TestIssuer tree | commitdiff
2021-04-20 Luke Kenneth Casso... add enable MMU option to issuer_verilog.py tree | commitdiff
2021-04-20 Luke Kenneth Casso... cannot pass in arguments to Core - must be done with... tree | commitdiff
2021-04-10 Cesar StraussAdd 1<<r3 test cases to TestIssuer tree | commitdiff
2021-04-06 Cesar StraussAdd a HDL test case, where we start at the middle of... tree | commitdiff
2021-04-03 Cesar StraussFix typo tree | commitdiff
2021-04-03 Cesar StraussAdd test case with all mask bits equal to zero tree | commitdiff
2021-04-03 Cesar StraussAdd a test case for integer single predication tree | commitdiff
2021-04-03 Cesar StraussEnable remaining disabled test cases tree | commitdiff
2021-03-30 Alain D D WilliamsMerge branch 'master' of git.libre-soc.org:soc tree | commitdiff
2021-03-30 Cesar StraussEnable VCOMPRESS test case tree | commitdiff
2021-03-30 Cesar StraussAdd new twin predication case tree | commitdiff
2021-03-30 Cesar StraussAdjust twin predication cases for the new syntax tree | commitdiff
2021-03-28 Luke Kenneth Casso... rather invasive reduction of SPR regfile size tree | commitdiff
2021-03-22 Cesar StraussAdd test cases for integer VCOMPRESS and VEXPAND tree | commitdiff
2021-03-21 Luke Kenneth Casso... adjust syntax of SVP64 predicate test cas tree | commitdiff
2021-03-21 Luke Kenneth Casso... naah. back to "sv." syntax for SVP64 assembly tree | commitdiff
2021-03-21 Cesar StraussAdd predication test case, initially disabled tree | commitdiff
2021-03-14 Luke Kenneth Casso... remove "sv." and replace with "sv" in all SVP64Asm tree | commitdiff
2021-03-11 Cesar StraussBring a few test cases from test_caller_64.py tree | commitdiff
2021-03-11 Cesar StraussTest case for two successive SV instructions tree | commitdiff
2021-03-09 Cesar StraussEnable VL==0 vector instruction skip test case tree | commitdiff
2021-03-08 Luke Kenneth Casso... correct comments in sv.add rc=1 tree | commitdiff
2021-03-07 Luke Kenneth Casso... add Rc=1 SVP64 unit test to svp64_cases.py tree | commitdiff
2021-03-06 Cesar StraussEnable the Simple-V loop test case tree | commitdiff
2021-03-02 Luke Kenneth Casso... comment out changing SPR 720 because 720 is not support... tree | commitdiff
2021-03-02 Luke Kenneth Casso... sort out SPR setting in MMU tree | commitdiff
2021-03-02 Luke Kenneth Casso... operating correctly, not directing MMU SPRs to SPR... tree | commitdiff
2021-03-02 Luke Kenneth Casso... must always set ok for writing out data otherwise it... tree | commitdiff
2021-02-26 Cesar StraussAdd a vector case with VL == 0 tree | commitdiff
2021-02-24 Tobias Platenupdate mmu testcase tree | commitdiff
2021-02-20 Luke Kenneth Casso... correct arguments, set microwatt_mmu=True, pass in... tree | commitdiff
2021-02-20 Luke Kenneth Casso... minor whitespace cleanup tree | commitdiff
2021-02-20 Tobias Platenmmu testcase: set MMU SPRs tree | commitdiff
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