Provide full name and email in copyright notice.
[soc.git] / src / soc / fu /
2020-09-03 Samuel A. Falvo IIProvide full name and email in copyright notice.
2020-09-02 Luke Kenneth Casso... when mtocrf FXM is 0, the CR has to be set to CR7
2020-09-02 Luke Kenneth Casso... fix bug in cmpli (and cmplw)
2020-09-02 Luke Kenneth Casso... sign-extend lhax needs 16-64, separate from lwax which...
2020-09-02 Luke Kenneth Casso... add bc ctr regression test when CTR=0 and CTR=1
2020-09-02 Luke Kenneth Casso... bug in carry32 handling in OP_CMP
2020-09-02 Luke Kenneth Casso... add cmpl regression test (one binary, one assembly)
2020-09-02 Luke Kenneth Casso... add cmpl microwatt 1.bin test, cmpl
2020-09-02 Luke Kenneth Casso... series of extensive modifications to fix long-standing...
2020-08-31 Luke Kenneth Casso... add XER to fastregs and "construct" it in mfspr/mtspr
2020-08-30 Luke Kenneth Casso... redo OP_CMP based on microwatt. L=1 had been ignored
2020-08-30 Luke Kenneth Casso... reversal of FXM mask for one-hot selection in OP_MTCR...
2020-08-30 Luke Kenneth Casso... tidyup on mul proof
2020-08-30 Luke Kenneth Casso... set mul post_stage o.ok only when needed, and fix xer_s...
2020-08-30 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-29 Samuel A. Falvo IIQualify XER_OV output in proof
2020-08-29 Samuel A. Falvo IIFix test breakage in MUL proofs
2020-08-29 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-29 Samuel A. Falvo IIBROKEN: xer_ov_o != dut.o.xer_ov.data ???!!!
2020-08-29 Luke Kenneth Casso... minor code-shuffle, comments
2020-08-29 Luke Kenneth Casso... slowly morphing towards using an XER bit-field selector...
2020-08-29 Samuel A. Falvo IIMUL pipeline formal proofs complete, I *think*.
2020-08-29 Samuel A. Falvo IIWIP: prep for 64-bit insns
2020-08-29 Luke Kenneth Casso... add additional CR regression tests
2020-08-29 Luke Kenneth Casso... CR FXM becomes a full mask.
2020-08-27 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-27 Luke Kenneth Casso... https://bugs.libre-soc.org/show_bug.cgi?id=476
2020-08-27 Luke Kenneth Casso... xer so is not being passed through to CR0
2020-08-27 Luke Kenneth Casso... augment addme test case to show bug #476
2020-08-27 Luke Kenneth Casso... add addze and addme uni tests
2020-08-27 Luke Kenneth Casso... oink, write_cr shiftrot record width was zero (??)
2020-08-27 Luke Kenneth Casso... sorting out shift_rot to use new output stage data...
2020-08-27 Luke Kenneth Casso... need to read SO if Rc=1
2020-08-27 Luke Kenneth Casso... reorg of SO handling related to CR0
2020-08-26 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-26 Luke Kenneth Casso... use sub-test in logical test_pipe_caller
2020-08-26 Luke Kenneth Casso... investigating div fsm and simulator bug
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-25 Jacob Lifshayfix broken remainder for div FSM
2020-08-25 Jacob Lifshayclean up formatting
2020-08-25 Luke Kenneth Casso... although shift-rot does not alter XER.so it still needs...
2020-08-24 Luke Kenneth Casso... add isel CR tests to run on qemu (confirmed working)
2020-08-24 Luke Kenneth Casso... make it easier to select FSM/Pipe DIV unit
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-23 Luke Kenneth Casso... update copyright notices to include additional primary...
2020-08-23 Luke Kenneth Casso... add load algebraic immediate unit test
2020-08-23 Luke Kenneth Casso... add algebraic ld tests lwax, lwaux
2020-08-23 Michael NolanAdd copyright to files in fu/ that I was the primary...
2020-08-23 Luke Kenneth Casso... multiply does not have invert_in, zero_a or invert_out
2020-08-22 Luke Kenneth Casso... rename invert_a to invert_in because logical inverts RB
2020-08-22 Luke Kenneth Casso... add extra div regression tests
2020-08-22 Luke Kenneth Casso... add eqv to logical unit test
2020-08-22 Luke Kenneth Casso... add nor and nand to unit test
2020-08-22 Luke Kenneth Casso... moved to div pipe temporarily in compunits
2020-08-22 Luke Kenneth Casso... bug in andc and orc, complement was taking place on...
2020-08-22 Luke Kenneth Casso... add andc and orc tests, failing because RB needs invers...
2020-08-22 Luke Kenneth Casso... modsd bug, https://bugs.libre-soc.org/show_bug.cgi...
2020-08-22 Luke Kenneth Casso... add regression test for nonzero addis
2020-08-22 Luke Kenneth Casso... r0 zero tests on addis, fails
2020-08-21 Samuel A. Falvo IIMUL pipeline WIP: mullw and mullwu covered.
2020-08-21 Samuel A. Falvo IIMUL pipeline: account for overflow flags. WIP
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-21 Samuel A. Falvo IIMUL pipeline proofs: mulli / mullw WIP.
2020-08-20 Samuel A. Falvo IIMUL pipeline proof: muldw(u)
2020-08-20 Samuel A. Falvo IIMUL pipeline proof: signed mulhw
2020-08-19 Luke Kenneth Casso... rename and document fields in shift_rot proof
2020-08-19 Luke Kenneth Casso... bit of a reorg of mul proof, tracking down missing
2020-08-19 Luke Kenneth Casso... move long mul tests to separate unit test
2020-08-19 Luke Kenneth Casso... use "Mask" class which is more gate-efficient than...
2020-08-19 Samuel A. Falvo IIWIP: OP_MUL proofs started.
2020-08-19 Luke Kenneth Casso... set up StageChain of 3 mul stages
2020-08-18 Cole Poirierfu/mul/test/test_pipe_caller.py test case_all_rb_close_...
2020-08-18 Luke Kenneth Casso... fix spr state test
2020-08-17 Luke Kenneth Casso... turn SelectableInt less/greater into signed versions.
2020-08-17 Luke Kenneth Casso... fix signed variants of cmp in alu
2020-08-17 Luke Kenneth Casso... add new cmp test for alu
2020-08-16 Luke Kenneth Casso... attempting to track down bug in litex bios memtest
2020-08-14 Luke Kenneth Casso... hrfid unit test sets up HSRR0 and HSRR1
2020-08-14 Luke Kenneth Casso... hack to get hrfid not to alter msr 51
2020-08-14 Luke Kenneth Casso... fix test_compunit.py after moving decoder rdflags function
2020-08-14 Luke Kenneth Casso... add hrfid unit test
2020-08-14 Luke Kenneth Casso... sort out instruction stop/cancel when adding a new...
2020-08-14 Luke Kenneth Casso... divide shiftrot pipeline into 2 (simple last)
2020-08-14 Luke Kenneth Casso... divide alu pipeline into 2 (simple last)
2020-08-14 Luke Kenneth Casso... divide logical pipe into 2 (simple phase last)
2020-08-11 Luke Kenneth Casso... reduce regfile ports by creating separate STATE regfile
2020-08-11 Luke Kenneth Casso... whoops fix change of variable (state) msr/pc
2020-08-10 Samuel A. Falvo IIWIP!! Make MUL pipeline proof run again.
2020-08-09 Luke Kenneth Casso... divwo case makes test_issuer stay busy!
2020-08-09 Luke Kenneth Casso... add extra divwo regression test
2020-08-08 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-08 Cole PoirierUpdate test case_mulli
2020-08-07 Cole PoirierUpdate test case_mulli
2020-08-07 Cole PoirierUpdate test case_mulli, I think it now works correctly
2020-08-07 Cole PoirierUpdate mulli to try to use immediates not registers
2020-08-06 Cole PoirierFix formatting
2020-08-06 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-06 Cole PoirierUpdate test case_all_rb_close_to_ov
2020-08-06 Cole PoirierUpdate test case_all_rb_close_to_ov
2020-08-06 Cole PoirierAdd special test for case_mulli, apply autopep8
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