big reorg on PowerDecoder2, actually Decode2Execute1Type
[soc.git] / src / soc / fu /
2020-07-05 Luke Kenneth Casso... big reorg on PowerDecoder2, actually Decode2Execute1Type
2020-07-05 Luke Kenneth Casso... check xer_out not xer_in
2020-07-05 Luke Kenneth Casso... sigh read and write xer detection, fix spr and trap...
2020-07-05 Luke Kenneth Casso... check spr1 in test spr compunit
2020-07-05 Luke Kenneth Casso... get/set slow spr in spr test_pipe_caller
2020-07-05 Luke Kenneth Casso... add first spr compunit test (not working yet)
2020-07-05 Luke Kenneth Casso... comment out SPR for now, needs SPR regfile
2020-07-05 Luke Kenneth Casso... add SPR compunit
2020-07-05 Luke Kenneth Casso... check NIA on trap fu test
2020-07-04 Luke Kenneth Casso... cater for illegal instruction (generates a trap)
2020-07-04 Luke Kenneth Casso... add sc back in
2020-07-04 Luke Kenneth Casso... comments in trap about exceptions using microcoding
2020-07-04 Luke Kenneth Casso... more updating spr1/spr2 to fast1/fast2
2020-07-04 Luke Kenneth Casso... more updating spr1/spr2 to fast1/fast2
2020-07-04 Luke Kenneth Casso... rename spr1/spr2 to fast1/fast2 in branch
2020-07-04 Luke Kenneth Casso... update trap docstring
2020-07-04 Luke Kenneth Casso... use new consts module
2020-07-04 Luke Kenneth Casso... sorting out trap fastregs
2020-07-04 Luke Kenneth Casso... sort out trap test reg checking
2020-07-04 Luke Kenneth Casso... rename spr1 to fast1 in trap data
2020-07-04 Luke Kenneth Casso... sorting out fast/spr naming
2020-07-04 Luke Kenneth Casso... oops initialise Function Unit class with idx
2020-07-04 Luke Kenneth Casso... add first cookie-cut test_trap_compunit.py
2020-07-04 Luke Kenneth Casso... debugging decoding of SPRs (fast)
2020-07-04 Luke Kenneth Casso... add spr test, add decode of spr in/out
2020-07-04 Luke Kenneth Casso... add spr main stage
2020-07-04 Luke Kenneth Casso... add spr input record
2020-07-04 Luke Kenneth Casso... add SPR pipeline
2020-07-04 Luke Kenneth Casso... reduce steps per stage to 8
2020-07-03 Luke Kenneth Casso... set only div/rem supported
2020-07-02 Luke Kenneth Casso... allow flexible selection of the types of ALUs
2020-07-02 Luke Kenneth Casso... fix unit tests due to change in using pspec
2020-07-02 Luke Kenneth Casso... allow ALU names to propagate through from FU to CompUni...
2020-07-02 Luke Kenneth Casso... name function unit ALUs
2020-07-02 Luke Kenneth Casso... comment out DIV unit for now
2020-07-02 Luke Kenneth Casso... increase combinatorial stages to 8
2020-07-02 Luke Kenneth Casso... reduce DIV radix to 1
2020-07-02 Luke Kenneth Casso... add DIV function unit to compunits
2020-07-02 Luke Kenneth Casso... add trap function unit into compunits
2020-07-01 Luke Kenneth Casso... whoops missed some cases in unit test changing ALUHelpers
2020-07-01 Luke Kenneth Casso... whoops swapped trap test instructions accidentally
2020-07-01 Luke Kenneth Casso... attempting to add SPRs to rfid test
2020-07-01 Luke Kenneth Casso... trap test check results
2020-07-01 Luke Kenneth Casso... add in trap compunit
2020-07-01 Luke Kenneth Casso... add rfid and td/tw trap test
2020-07-01 Luke Kenneth Casso... continue debugging trap pipeline
2020-07-01 Luke Kenneth Casso... debugging trap pipeline
2020-07-01 Luke Kenneth Casso... start running trap unit test, fixing errors
2020-06-30 Luke Kenneth Casso... code-morph on div pipeline
2020-06-29 Luke Kenneth Casso... add README for fu directory
2020-06-29 Luke Kenneth Casso... use correct ALUHelpers in div test
2020-06-29 Luke Kenneth Casso... sort out syntax errors in div
2020-06-29 Luke Kenneth Casso... first unit test for div
2020-06-28 Luke Kenneth Casso... got Pi2LSUI FSM working
2020-06-27 Luke Kenneth Casso... make Memory accessible via TestSRAMBareLoadStoreUnit
2020-06-27 Luke Kenneth Casso... increase (double) address width in TstL0CacheBuffer
2020-06-22 Luke Kenneth Casso... simplified L0CacheBuffer down to a "PortInterface Arbiter"
2020-06-19 Luke Kenneth Casso... whitespace update
2020-06-18 Jacob Lifshaydiv pipe completed except for tests
2020-06-18 Jacob Lifshayfinish code to calculate the 64-bit output of the div...
2020-06-18 Jacob Lifshayactually remove todo comment for manually checking...
2020-06-18 Jacob LifshayMerge branch 'master' of ssh://git.libre-riscv.org...
2020-06-18 Jacob Lifshayfix bug and manually check div overflow code against...
2020-06-18 Luke Kenneth Casso... use while / exception in test_compunit loop
2020-06-18 Jacob Lifshayworking on adding rest of stage classes for div pipeline
2020-06-17 Luke Kenneth Casso... decoding assembly instruction name, move to separate...
2020-06-17 Luke Kenneth Casso... get fu compunit test to use ISACaller instruction-memory
2020-06-17 Luke Kenneth Casso... start to add in independent execution into ISACaller
2020-06-17 Luke Kenneth Casso... use an independent power decoder in ISACaller
2020-06-16 Luke Kenneth Casso... update popcount docstring
2020-06-15 Luke Kenneth Casso... move setup/check memory into helper functions for use...
2020-06-15 Luke Kenneth Casso... whoops LDSTCompUnit was identified as a Function.ALU...
2020-06-15 Luke Kenneth Casso... add in TstL0CacheBuffer but disable temporarily
2020-06-14 Luke Kenneth Casso... add optional LDSTFunctionUnit to compunits
2020-06-14 Luke Kenneth Casso... unit tests showing byte-reverse works
2020-06-14 Luke Kenneth Casso... reasonably certain that the careful and slow use of...
2020-06-12 Luke Kenneth Casso... update ld/st test to see what is going on
2020-06-12 Luke Kenneth Casso... tracking down what looks like an error in the Simulator...
2020-06-12 Luke Kenneth Casso... debug printout of sim and hardware memory, shows mismat...
2020-06-12 Luke Kenneth Casso... use ALUHelpers in LDSTCompUnit test
2020-06-11 Luke Kenneth Casso... some ugly hacks that get LD/ST immediate working
2020-06-11 Luke Kenneth Casso... even more complexity in CompALUMulti, to deal with...
2020-06-11 Luke Kenneth Casso... must distinguish between rd/write xer_ca sim helpers
2020-06-11 Luke Kenneth Casso... fixing get_rd_sim_xer_ca, has to only read carry if...
2020-06-11 Luke Kenneth Casso... yield needed for unit tests to work (has to go)
2020-06-11 Luke Kenneth Casso... read and write version of get_sim_xer_ca are different
2020-06-11 Luke Kenneth Casso... use ALUHelpers in shift_rot
2020-06-11 Luke Kenneth Casso... add fast spr1/2 sim ALUHelpers
2020-06-11 Luke Kenneth Casso... rename get_sim_cr_a to get_wr_sim_cr_a for now
2020-06-10 Luke Kenneth Casso... whitespace
2020-06-10 Luke Kenneth Casso... link ST.go directly to ST.rel
2020-06-10 Luke Kenneth Casso... add link to bug 361 in FU test
2020-06-10 Luke Kenneth Casso... TODO on RA immediate-zero mode
2020-06-10 Luke Kenneth Casso... re-do cookie-cut of alu test_pipe_caller.py over to...
2020-06-10 Luke Kenneth Casso... use ALUHelpers in output stage of test_pipe_caller
2020-06-10 Luke Kenneth Casso... use sim-get helpers in ALU input fetch
2020-06-10 Luke Kenneth Casso... use ALUHelpers in output phase of test_alu_compunit.py
2020-06-10 Luke Kenneth Casso... continue ALUHelpers check alu outputs code-morph
2020-06-10 Luke Kenneth Casso... code-morph ALU output test check phase
2020-06-10 Luke Kenneth Casso... starting on alu output check
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