2020-10-06 |
Jacob Lifshay | add workaround for nmigen bug #502 |
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2020-10-06 |
Jacob Lifshay | add modsw regression |
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2020-10-06 |
Jacob Lifshay | add test case for divweu regression |
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2020-10-06 |
Jacob Lifshay | print regs in hex |
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2020-10-05 |
Luke Kenneth Casso... | add debug / investigation print statements |
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2020-10-05 |
Jacob Lifshay | `deepcopy` from cache instead of recreating parsers... |
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2020-10-05 |
Jacob Lifshay | format code |
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2020-10-05 |
Cole Poirier | icache.py fix ispow2() util fn per https://bugs.libre... |
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2020-10-05 |
Luke Kenneth Casso... | whoops fix syntax error |
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2020-10-05 |
Luke Kenneth Casso... | whoops fix syntax error |
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2020-10-05 |
Luke Kenneth Casso... | return test rather than "if test return True else False" |
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2020-10-05 |
Luke Kenneth Casso... | whitespace |
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2020-10-05 |
Luke Kenneth Casso... | whitespace |
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2020-10-05 |
Cole Poirier | icache.py add python asserts that were a TODO commented... |
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2020-10-05 |
Cole Poirier | icache.py fix formatting, mostly due to reduced indenta... |
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2020-10-05 |
Cole Poirier | icache.py remove comment that contained the entirety... |
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2020-10-05 |
Cole Poirier | icache.py move icache_miss WAIT_ACK FSM state into... |
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2020-10-05 |
Cole Poirier | icache.py move icache_miss CLR_TAG FSM state into metho... |
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2020-10-05 |
Cole Poirier | icache.py move icache_miss IDLE FSM state into method... |
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2020-10-05 |
Jacob Lifshay | simplify create_args |
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2020-10-05 |
Jacob Lifshay | Sort returned variables to make sure `overflow` is... |
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2020-10-05 |
Jacob Lifshay | format caller.py |
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2020-10-04 |
Jacob Lifshay | change div FSM pipeline unit to not have a combinatoria... |
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2020-10-04 |
Luke Kenneth Casso... | significant reorg of the litex pinspecs to use pinmux... |
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2020-10-04 |
Luke Kenneth Casso... | submodule update |
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2020-10-04 |
Luke Kenneth Casso... | remove ls180io import |
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2020-10-04 |
Luke Kenneth Casso... | move ls180io.py back into ls180.py |
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2020-10-03 |
Luke Kenneth Casso... | allow i2c to be routed via JTAG |
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2020-10-03 |
Luke Kenneth Casso... | nope. put it back and connect to platform pads in... |
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2020-10-03 |
Luke Kenneth Casso... | move iopad litex creation to ls180soc.py |
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2020-10-03 |
Luke Kenneth Casso... | minor reorg on JTAG, allow alternative pinset dict... |
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2020-10-03 |
Jacob Lifshay | add regression testcase |
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2020-10-02 |
Cole Poirier | icache.py add req_hit_way as arg to icache_comb, actual... |
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2020-10-01 |
Cole Poirier | icache.py add missing comb signal assignments per https... |
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2020-10-01 |
Luke Kenneth Casso... | arg CacheRam read output needs delay by 1 cycle |
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2020-10-01 |
Luke Kenneth Casso... | do not pass cache row array around, just the current row |
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2020-10-01 |
Luke Kenneth Casso... | revert bug in icache wishbone ack |
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2020-10-01 |
Luke Kenneth Casso... | add clksel, pll to ls180 |
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2020-10-01 |
Luke Kenneth Casso... | create dummy PLL block, connect up to core and clock... |
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2020-10-01 |
Cesar Strauss | Add GTKWave document to test_compunit_fsm |
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2020-09-30 |
Luke Kenneth Casso... | add I2C into ls180 |
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2020-09-30 |
Luke Kenneth Casso... | add ASIC version of I2C Master |
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2020-09-30 |
Luke Kenneth Casso... | clean up row store and wb adr in icache |
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2020-09-30 |
Luke Kenneth Casso... | hmm only set wishbone address if ack is actually received |
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2020-09-30 |
Luke Kenneth Casso... | add more debug prints in icache |
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2020-09-30 |
Luke Kenneth Casso... | remove more reviewed comments |
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2020-09-30 |
Luke Kenneth Casso... | remove reviewed comments |
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2020-09-30 |
Luke Kenneth Casso... | comb on wr_index not sync |
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2020-09-30 |
Luke Kenneth Casso... | start removing reviewed comments |
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2020-09-30 |
Luke Kenneth Casso... | use same constant name (confusing otherwise) |
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2020-09-30 |
Luke Kenneth Casso... | need asserts |
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2020-09-30 |
Luke Kenneth Casso... | halve the number of icache lines for now |
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2020-09-30 |
Luke Kenneth Casso... | use Repl rather than for-loop to copy bit |
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2020-09-30 |
Luke Kenneth Casso... | move loop invariant test out of loop |
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2020-09-30 |
Luke Kenneth Casso... | reduce size of ilang file by a factor of FIVE |
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2020-09-30 |
Luke Kenneth Casso... | store tag in temp signal |
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2020-09-30 |
Luke Kenneth Casso... | reduce gate usage by getting cache row only not entire... |
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2020-09-30 |
Luke Kenneth Casso... | fix read_tag to use word_select correctly |
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2020-09-30 |
Luke Kenneth Casso... | forgot to add PLRUs as submodules |
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2020-09-29 |
Cole Poirier | icache.py fix combinatorial loop with by testing temp... |
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2020-09-29 |
Cole Poirier | icache.py fix is_last_row_addr, get_next_row_addr |
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2020-09-29 |
Cole Poirier | icache.py trying to sort out test failure, added r... |
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2020-09-29 |
Cole Poirier | icache.py fix test stbs_done signal, not stbs_zero... |
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2020-09-29 |
Cole Poirier | icache.py fix rarange |
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2020-09-29 |
Cole Poirier | icache.py fixed numerous bugs as specified by lkcl... |
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2020-09-28 |
Cole Poirier | icache.py use d_out as input to assignment instead... |
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2020-09-28 |
Luke Kenneth Casso... | reduce not-connected IO pins |
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2020-09-28 |
Luke Kenneth Casso... | missing pspec |
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2020-09-28 |
Luke Kenneth Casso... | connect SDRAM dqm to wrdata_mask |
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2020-09-28 |
Luke Kenneth Casso... | lots of sorting out iopads |
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2020-09-28 |
Luke Kenneth Casso... | add "nocore" option to build verilog |
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2020-09-28 |
Luke Kenneth Casso... | switch off internal gpio (testing) |
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2020-09-28 |
Luke Kenneth Casso... | rewrite ilang file after litex ls180 build |
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2020-09-28 |
Luke Kenneth Casso... | had to over-ride the wishbone functions on C4M TAP |
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2020-09-27 |
Cole Poirier | icache.py fix translation mistake |
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2020-09-27 |
Cesar Strauss | Convert yet another few tests to be able to use latest... |
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2020-09-27 |
Luke Kenneth Casso... | add Makefile for creating ls180.il |
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2020-09-27 |
Luke Kenneth Casso... | rename sys_clk_i to clk_24_i |
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2020-09-27 |
Luke Kenneth Casso... | add clock selection mechanism |
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2020-09-26 |
Luke Kenneth Casso... | DMI-to-JTAG needed to be "sync" to get ack/resp right |
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2020-09-26 |
Luke Kenneth Casso... | do not use simdec2 in test_pipe_caller |
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2020-09-26 |
Luke Kenneth Casso... | fix annoying alu test_pipe_caller bug, missing asmcode |
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2020-09-26 |
Luke Kenneth Casso... | add alternative PowerDecode2 to branch test_pipe_caller |
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2020-09-26 |
Cesar Strauss | Convert a few more tests to be able to use cxxsim |
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2020-09-26 |
Luke Kenneth Casso... | try svf test of DMI MSR |
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2020-09-26 |
Luke Kenneth Casso... | make check of LDSTMode.update conditional in PowerDecoder2 |
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2020-09-26 |
Luke Kenneth Casso... | add ls180io.py |
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2020-09-26 |
Luke Kenneth Casso... | add openocd script to fire off svf test |
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2020-09-26 |
Luke Kenneth Casso... | get openocd svf test running, replicating jtag test |
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2020-09-26 |
Luke Kenneth Casso... | put test into "server" mode for connecting with openocd |
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2020-09-26 |
Luke Kenneth Casso... | create client-server version of jtag debug unit test |
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2020-09-26 |
Luke Kenneth Casso... | create client-server version of jtag debug unit test |
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2020-09-26 |
Luke Kenneth Casso... | class-ify jtagremote |
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2020-09-26 |
Luke Kenneth Casso... | send/receive jtagremote protocol |
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2020-09-26 |
Luke Kenneth Casso... | basic client/server socket example |
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2020-09-26 |
Luke Kenneth Casso... | add openocd configs |
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2020-09-26 |
Luke Kenneth Casso... | reduce sdram pins to smaller address and only 1 cs_n |
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2020-09-26 |
Luke Kenneth Casso... | only enable pads connections for ls180 for now |
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2020-09-25 |
Cole Poirier | icache.py fix several subtle bugs that were lines that... |
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2020-09-25 |
Cole Poirier | wb_types.py add reset value of 0b11111111 for WBSelType... |
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