2020-07-06 |
Cesar Strauss | Simplify waiting loops |
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2020-07-06 |
Cesar Strauss | Finally add some well needed comments |
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2020-07-06 |
Cesar Strauss | Simplify waiting loops |
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2020-07-06 |
Cesar Strauss | Add some wait states in each process |
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2020-07-06 |
Cesar Strauss | Negate inputs after use |
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2020-07-06 |
Cesar Strauss | Add other tests |
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2020-07-06 |
Cesar Strauss | Implement receiver |
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2020-07-06 |
Cesar Strauss | Implement sender. |
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2020-07-06 |
Cesar Strauss | Begin a new parallel test |
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2020-07-05 |
Luke Kenneth Casso... | add mtmsr tests (fail) |
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2020-07-05 |
Luke Kenneth Casso... | check trap compunit output properly |
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2020-07-05 |
Luke Kenneth Casso... | check msr in trap test, fix OP_RFID |
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2020-07-05 |
Luke Kenneth Casso... | add an illegal instruction trap test |
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2020-07-05 |
Luke Kenneth Casso... | set up a trap function for microcode override |
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2020-07-05 |
Luke Kenneth Casso... | big reorg on PowerDecoder2, actually Decode2Execute1Type |
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2020-07-05 |
Luke Kenneth Casso... | stop debug output in power_decoder |
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2020-07-05 |
Luke Kenneth Casso... | comments in power_regspec_map.py |
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2020-07-05 |
Luke Kenneth Casso... | comment on spr2, not needed |
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2020-07-05 |
Luke Kenneth Casso... | check xer_out not xer_in |
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2020-07-05 |
Luke Kenneth Casso... | split out Decode2ToExecuteType fields involving registers |
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2020-07-05 |
Luke Kenneth Casso... | sigh read and write xer detection, fix spr and trap... |
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2020-07-05 |
Luke Kenneth Casso... | check spr1 in test spr compunit |
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2020-07-05 |
Luke Kenneth Casso... | get/set slow spr in spr test_pipe_caller |
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2020-07-05 |
Luke Kenneth Casso... | add first spr compunit test (not working yet) |
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2020-07-05 |
Luke Kenneth Casso... | add SPR test case, commented out for now |
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2020-07-05 |
Luke Kenneth Casso... | move valid signal out of Decode2ToExecute1Type and... |
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2020-07-05 |
Luke Kenneth Casso... | add slow spr regfile regspec support |
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2020-07-05 |
Luke Kenneth Casso... | remap SPR PowerISA numbers to internal SPR enum |
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2020-07-05 |
Luke Kenneth Casso... | comment out SPR for now, needs SPR regfile |
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2020-07-05 |
Luke Kenneth Casso... | add SPR compunit |
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2020-07-05 |
Luke Kenneth Casso... | missing initialisation of disasm_start |
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2020-07-05 |
Luke Kenneth Casso... | check NIA on trap fu test |
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2020-07-05 |
Luke Kenneth Casso... | OP_RFID needs to read SRR0/1, OP_SC needs to write |
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2020-07-05 |
Luke Kenneth Casso... | fix qemu trap test |
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2020-07-04 |
Luke Kenneth Casso... | cater for illegal instruction (generates a trap) |
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2020-07-04 |
Luke Kenneth Casso... | add sc back in |
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2020-07-04 |
Luke Kenneth Casso... | comments in trap about exceptions using microcoding |
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2020-07-04 |
Luke Kenneth Casso... | add pspec to test_core.py |
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2020-07-04 |
Luke Kenneth Casso... | add pspec to test_core.py |
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2020-07-04 |
Luke Kenneth Casso... | more rename spr1/spr2 to fast1/fast2 |
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2020-07-04 |
Luke Kenneth Casso... | whitespace |
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2020-07-04 |
Luke Kenneth Casso... | more updating spr1/spr2 to fast1/fast2 |
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2020-07-04 |
Luke Kenneth Casso... | more updating spr1/spr2 to fast1/fast2 |
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2020-07-04 |
Luke Kenneth Casso... | rename spr1/spr2 to fast1/fast2 in branch |
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2020-07-04 |
Luke Kenneth Casso... | update trap docstring |
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2020-07-04 |
Luke Kenneth Casso... | use new consts module |
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2020-07-04 |
Luke Kenneth Casso... | sorting out trap fastregs |
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2020-07-04 |
Luke Kenneth Casso... | sort out trap test reg checking |
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2020-07-04 |
Luke Kenneth Casso... | resolve spr names in ISACaller |
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2020-07-04 |
Luke Kenneth Casso... | rename spr1 to fast1 in trap data |
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2020-07-04 |
Luke Kenneth Casso... | sorting out fast/spr naming |
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2020-07-04 |
Luke Kenneth Casso... | oops initialise Function Unit class with idx |
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2020-07-04 |
Luke Kenneth Casso... | add first cookie-cut test_trap_compunit.py |
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2020-07-04 |
Luke Kenneth Casso... | add gitignores |
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2020-07-04 |
Luke Kenneth Casso... | debugging decoding of SPRs (fast) |
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2020-07-04 |
Luke Kenneth Casso... | add spr test, add decode of spr in/out |
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2020-07-04 |
Luke Kenneth Casso... | add spr main stage |
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2020-07-04 |
Luke Kenneth Casso... | add spr input record |
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2020-07-04 |
Luke Kenneth Casso... | add SPR pipeline |
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2020-07-04 |
Luke Kenneth Casso... | reduce steps per stage to 8 |
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2020-07-03 |
Luke Kenneth Casso... | set only div/rem supported |
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2020-07-02 |
Luke Kenneth Casso... | allow flexible selection of the types of ALUs |
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2020-07-02 |
Luke Kenneth Casso... | fix unit tests due to change in using pspec |
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2020-07-02 |
Luke Kenneth Casso... | use Mock class (more convenient) |
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2020-07-02 |
Luke Kenneth Casso... | allow ALU names to propagate through from FU to CompUni... |
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2020-07-02 |
Luke Kenneth Casso... | name function unit ALUs |
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2020-07-02 |
Luke Kenneth Casso... | comment out DIV unit for now |
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2020-07-02 |
Luke Kenneth Casso... | increase combinatorial stages to 8 |
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2020-07-02 |
Luke Kenneth Casso... | reduce DIV radix to 1 |
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2020-07-02 |
Luke Kenneth Casso... | add DIV function unit to compunits |
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2020-07-02 |
Luke Kenneth Casso... | add trap function unit into compunits |
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2020-07-02 |
Luke Kenneth Casso... | add bare wishbone option to TestIssuer, sort out ports |
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2020-07-02 |
Luke Kenneth Casso... | use single-arg pspec for TestIssuer and Core |
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2020-07-02 |
Cesar Strauss | Present the ALU result only when valid_o is active |
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2020-07-01 |
Luke Kenneth Casso... | whoops missed some cases in unit test changing ALUHelpers |
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2020-07-01 |
Luke Kenneth Casso... | minor reorg on how Bus and Config classes are set up |
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2020-07-01 |
Luke Kenneth Casso... | whoops swapped trap test instructions accidentally |
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2020-07-01 |
Luke Kenneth Casso... | print out msr for debug |
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2020-07-01 |
Luke Kenneth Casso... | attempting to add SPRs to rfid test |
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2020-07-01 |
Luke Kenneth Casso... | add OP_SC |
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2020-07-01 |
Luke Kenneth Casso... | trap test check results |
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2020-07-01 |
Luke Kenneth Casso... | add name "test_issuer" to ilang conversion |
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2020-07-01 |
Luke Kenneth Casso... | add in trap compunit |
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2020-07-01 |
Luke Kenneth Casso... | add rfid and td/tw trap test |
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2020-07-01 |
Luke Kenneth Casso... | continue debugging trap pipeline |
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2020-07-01 |
Luke Kenneth Casso... | debugging trap pipeline |
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2020-07-01 |
Luke Kenneth Casso... | start running trap unit test, fixing errors |
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2020-06-30 |
Luke Kenneth Casso... | add lte ltu for use by twi and other trap functions |
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2020-06-30 |
Luke Kenneth Casso... | add in pseudocode keyword into mdwn isa files |
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2020-06-30 |
Luke Kenneth Casso... | code-morph on div pipeline |
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2020-06-29 |
Luke Kenneth Casso... | add README for fu directory |
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2020-06-29 |
Luke Kenneth Casso... | use correct ALUHelpers in div test |
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2020-06-29 |
Luke Kenneth Casso... | sort out syntax errors in div |
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2020-06-29 |
Luke Kenneth Casso... | first unit test for div |
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2020-06-29 |
Luke Kenneth Casso... | add ignore for parsetab.py |
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2020-06-29 |
Luke Kenneth Casso... | add autogenerated do not commit comment |
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2020-06-29 |
Luke Kenneth Casso... | separate out divide by zero cases |
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2020-06-29 |
Luke Kenneth Casso... | update OV and OV32 ISACaller flags if overflow occurs |
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2020-06-29 |
Luke Kenneth Casso... | attempting to add overflow setting in ISACaller |
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2020-06-29 |
Luke Kenneth Casso... | whoops, hex parser digits are in multiples of 4 bits |
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