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reconfigureable PortInterface testing now possible
[soc.git]
/
src
/
2020-06-27
Luke Kenneth Casso...
reconfigureable PortInterface testing now possible
tree
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commitdiff
2020-06-26
Luke Kenneth Casso...
name issue in Pi2LSUI
tree
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commitdiff
2020-06-26
Luke Kenneth Casso...
whitespace and imports
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commitdiff
2020-06-26
Luke Kenneth Casso...
whitespace
tree
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commitdiff
2020-06-26
Luke Kenneth Casso...
slight reorg on test_pi2ls.py
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commitdiff
2020-06-26
Luke Kenneth Casso...
correct address in pi2ls
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commitdiff
2020-06-26
Luke Kenneth Casso...
oops forgot to initialise base class of TestMemLoadStor...
tree
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commitdiff
2020-06-26
Luke Kenneth Casso...
add in LenExpand shift/mask
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commitdiff
2020-06-26
Luke Kenneth Casso...
add quick test showing Pi2LSUI not quite reading/writing to
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commitdiff
2020-06-26
Luke Kenneth Casso...
remove extraneous yields
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commitdiff
2020-06-26
Michael Nolan
Modify pi2ls so it passes the portinterface unit tests
tree
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commitdiff
2020-06-26
Luke Kenneth Casso...
set address ok and fix unit test to check it properly
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commitdiff
2020-06-26
Luke Kenneth Casso...
add pi.busy_o connection, increase to 64 bit
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commitdiff
2020-06-26
Luke Kenneth Casso...
unit test broken is ok :)
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commitdiff
2020-06-26
Luke Kenneth Casso...
set pi.ld.ok to 1 if pi.is_ld_i is set
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commitdiff
2020-06-26
Michael Nolan
Move tests for pimem to new file, add ability to test...
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commitdiff
2020-06-26
Luke Kenneth Casso...
load/store unit test needed to wait for busy_o
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commitdiff
2020-06-26
Luke Kenneth Casso...
whitespace
tree
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commitdiff
2020-06-26
Luke Kenneth Casso...
clean up output from BareLoadStoreUnit
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commitdiff
2020-06-26
Luke Kenneth Casso...
halve the test memory size again
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commitdiff
2020-06-26
Luke Kenneth Casso...
shrink test memory size down to only 64 words
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commitdiff
2020-06-26
Luke Kenneth Casso...
investigating why write-enable not getting passed through
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commitdiff
2020-06-26
Luke Kenneth Casso...
whoops forgot to call parent elaborate
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commitdiff
2020-06-26
Luke Kenneth Casso...
add test of SRAM through wishbone bus
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commitdiff
2020-06-26
Luke Kenneth Casso...
code-morph which redirects lsmem unit test through...
tree
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commitdiff
2020-06-26
Luke Kenneth Casso...
add a test SRAM that lives behind a minerva LoadStoreUn...
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commitdiff
2020-06-26
Luke Kenneth Casso...
dynamically specify wishbone layout (no longer hardcode...
tree
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commitdiff
2020-06-26
Luke Kenneth Casso...
add reconfigureable Load/Store class
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commitdiff
2020-06-26
Luke Kenneth Casso...
extra parameterification of minerva LoadStoreUnits
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commitdiff
2020-06-25
Luke Kenneth Casso...
allow Pi2LSUI to accept incoming PortInterface and...
tree
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commitdiff
2020-06-25
Luke Kenneth Casso...
add extra parameter, mask_wid, to TestMemLoadStoreUnit
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commitdiff
2020-06-25
Luke Kenneth Casso...
start connecting up Pi2LSUI
tree
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commitdiff
2020-06-25
Luke Kenneth Casso...
add LenExpand module, tidyup on docstring
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commitdiff
2020-06-25
Luke Kenneth Casso...
add beginnings of Pi2LSUI
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commitdiff
2020-06-25
Luke Kenneth Casso...
add attempt at mapping between PortInterface and LoadSt...
tree
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commitdiff
2020-06-25
Luke Kenneth Casso...
rename LoadStoreInterface signals to include _i and...
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commitdiff
2020-06-25
Luke Kenneth Casso...
whitespace
tree
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commitdiff
2020-06-24
Michael Nolan
Revert "modify PortInterface so subfields include the...
tree
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commitdiff
2020-06-24
Michael Nolan
Update comments for LoadStoreUnitInterface
tree
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commitdiff
2020-06-24
Michael Nolan
Have lsmem handle stall and valid signals correctly
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commitdiff
2020-06-24
Michael Nolan
Update comments on LoadStoreUnitInterface again
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commitdiff
2020-06-24
Michael Nolan
Update comments on LoadStoreUnitInterface
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commitdiff
2020-06-24
Michael Nolan
Add handling of byte reads and writes
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commitdiff
2020-06-24
Michael Nolan
Add more complete testbench for lsmem.py
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commitdiff
2020-06-24
Michael Nolan
Super basic first try of testmem with load store unit...
tree
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commitdiff
2020-06-24
Luke Kenneth Casso...
move comments to minerva LoadStoreInterface
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commitdiff
2020-06-24
Luke Kenneth Casso...
import minerva and use LoadStoreUnitInterface
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commitdiff
2020-06-24
Michael Nolan
Add specification for load store interface
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commitdiff
2020-06-23
Michael Nolan
modify PortInterface so subfields include the port...
tree
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commitdiff
2020-06-23
Luke Kenneth Casso...
annoying error in latest nmigen
tree
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commitdiff
2020-06-23
Luke Kenneth Casso...
TstL0CacheBuffer returns array of ports differently now
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commitdiff
2020-06-22
Luke Kenneth Casso...
remove unused module
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commitdiff
2020-06-22
Luke Kenneth Casso...
simplified L0CacheBuffer down to a "PortInterface Arbiter"
tree
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commitdiff
2020-06-22
Luke Kenneth Casso...
add TestMemoryPortInterface class which is designed...
tree
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commitdiff
2020-06-22
Luke Kenneth Casso...
comments for LDST CompUnit test
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commitdiff
2020-06-22
Luke Kenneth Casso...
enable byte-reverse in CompLDSTUnit test
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commitdiff
2020-06-22
Luke Kenneth Casso...
remove CompLDSTOpSubset, replace with just data_len.
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commitdiff
2020-06-22
Luke Kenneth Casso...
move BE/LE byte-reverse into LDSTCompUnit
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commitdiff
2020-06-20
Luke Kenneth Casso...
expand Memory width to 64 and granularity to 16 in...
tree
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commitdiff
2020-06-20
Luke Kenneth Casso...
add asserts to check data output is correct
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commitdiff
2020-06-20
Luke Kenneth Casso...
add test_sram_wishbone.py
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commitdiff
2020-06-20
colepoirier
Add code, commented-out, for TRAP so as to not break...
tree
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commitdiff
2020-06-19
Luke Kenneth Casso...
whitespace update
tree
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commitdiff
2020-06-19
Luke Kenneth Casso...
move trunc_div and trunc_rem to nmutil
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commitdiff
2020-06-19
Luke Kenneth Casso...
add comments on trunc_div and trunc_rem
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commitdiff
2020-06-19
Luke Kenneth Casso...
add divide-by-zero test to test_div_sim.py
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commitdiff
2020-06-19
Luke Kenneth Casso...
add docstring comment for SelectableInt
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commitdiff
2020-06-19
Luke Kenneth Casso...
add test_0_moduw and correct name to trunc_rem
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commitdiff
2020-06-19
Luke Kenneth Casso...
add abs SelectableInt unit test (very quick)
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commitdiff
2020-06-19
Luke Kenneth Casso...
add SelectableInt.abs
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commitdiff
2020-06-19
Luke Kenneth Casso...
add another bad hack in parser.py which identifies...
tree
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commitdiff
2020-06-19
Luke Kenneth Casso...
add in really bad hack which calls trunc_div or trunc_mod
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commitdiff
2020-06-19
Luke Kenneth Casso...
add trunc_div and trunch_rem to decoder helpers
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commitdiff
2020-06-19
Luke Kenneth Casso...
auto-assign needs to use concat / selectconcat
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commitdiff
2020-06-19
Luke Kenneth Casso...
whoops detected page name wrong, for special case fixed...
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commitdiff
2020-06-19
Luke Kenneth Casso...
bit of a mess. getting carry recognised and output...
tree
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commitdiff
2020-06-19
Luke Kenneth Casso...
add auto-assign mode detecting uninitialised variable...
tree
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commitdiff
2020-06-19
Luke Kenneth Casso...
div needs to be floordiv
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commitdiff
2020-06-19
Luke Kenneth Casso...
add true and floor div to SelectableInt
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commitdiff
2020-06-19
Luke Kenneth Casso...
add simulator test for divw
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commitdiff
2020-06-19
Luke Kenneth Casso...
do mix-in for test_sim.py so that jacob can write some...
tree
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commitdiff
2020-06-19
Luke Kenneth Casso...
add TODO comments to upgrade L0CacheBuffer to a new...
tree
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commitdiff
2020-06-19
Luke Kenneth Casso...
parameterise LoadStoreUnitInterface to be expandable
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commitdiff
2020-06-18
Jacob Lifshay
div pipe completed except for tests
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commitdiff
2020-06-18
Jacob Lifshay
finish code to calculate the 64-bit output of the div...
tree
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commitdiff
2020-06-18
Jacob Lifshay
actually remove todo comment for manually checking...
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commitdiff
2020-06-18
Jacob Lifshay
Merge branch 'master' of ssh://git.libre-riscv.org...
tree
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commitdiff
2020-06-18
Jacob Lifshay
fix bug and manually check div overflow code against...
tree
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commitdiff
2020-06-18
Luke Kenneth Casso...
enable general test cases in test_issuer
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commitdiff
2020-06-18
Luke Kenneth Casso...
got loop example operational by noting when PC fastreg...
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commitdiff
2020-06-18
Luke Kenneth Casso...
use different way to pass instructions to test_issuer...
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commitdiff
2020-06-18
Luke Kenneth Casso...
debugging test_issuer.py general test cases
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commitdiff
2020-06-18
Luke Kenneth Casso...
get instructions immediately from assembly code
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commitdiff
2020-06-18
Luke Kenneth Casso...
move test_sim.py unit tests to different class (split)
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commitdiff
2020-06-18
Luke Kenneth Casso...
slightly hacky way to keep an eye on the PC
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commitdiff
2020-06-18
Luke Kenneth Casso...
whoops generate core ilang not TestIssuer
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commitdiff
2020-06-18
Luke Kenneth Casso...
use while / exception in test_compunit loop
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commitdiff
2020-06-18
Luke Kenneth Casso...
investigating mtocrf/mtcrf issue
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commitdiff
2020-06-18
Jacob Lifshay
working on adding rest of stage classes for div pipeline
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commitdiff
2020-06-17
Luke Kenneth Casso...
add bug reference to mtocrf/mtcrf name decoding
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commitdiff
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