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Fix bug in rotator preventing use of 64 bit rlcl/r
[soc.git]
/
src
/
2020-05-13
Michael Nolan
Fix bug in rotator preventing use of 64 bit rlcl/r
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commitdiff
2020-05-13
Luke Kenneth Casso...
add TODO placeholders for popcount and parity
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commitdiff
2020-05-13
Luke Kenneth Casso...
minor tidyup
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commitdiff
2020-05-13
Luke Kenneth Casso...
comments on ALU pipeline
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2020-05-13
Luke Kenneth Casso...
update comment on Logical pipeline
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2020-05-13
Luke Kenneth Casso...
remove Logical operations from ALU pipeline
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2020-05-13
Luke Kenneth Casso...
split out Logical operations into separate pipeline
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commitdiff
2020-05-13
Luke Kenneth Casso...
comments (and whitespace
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commitdiff
2020-05-13
Michael Nolan
Fix too wide bitfield being selected for opcode 30
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commitdiff
2020-05-13
Michael Nolan
Fix weirdness with rldicl and friends in test_caller.py
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commitdiff
2020-05-13
Michael Nolan
Add support for OP_EXTS
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commitdiff
2020-05-13
Luke Kenneth Casso...
restore field decoders (works with BE/LE) in rotator
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commitdiff
2020-05-13
Luke Kenneth Casso...
minor cleanup of shift_rot main_stage
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commitdiff
2020-05-13
Michael Nolan
Add missing input stage and pipe_data
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commitdiff
2020-05-13
Luke Kenneth Casso...
simplift right_mask and left_mask rotator sub-functions...
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commitdiff
2020-05-13
Michael Nolan
Fix bug with ROTL32 helper
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commitdiff
2020-05-13
Michael Nolan
Somewhat working now?
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commitdiff
2020-05-13
Michael Nolan
Integrate rotator.py into shift_rot unit
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commitdiff
2020-05-13
Michael Nolan
Update cmp test in test_caller.py
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commitdiff
2020-05-13
Michael Nolan
Add assertions to ALU and shift_rot test that the instr...
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commitdiff
2020-05-13
Michael Nolan
Add SHIFT_ROT FU
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commitdiff
2020-05-13
Michael Nolan
Modify alu test to put reg1 *OR* reg3 into alu input A
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commitdiff
2020-05-13
Michael Nolan
Update TODO
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commitdiff
2020-05-13
Luke Kenneth Casso...
remove operand c from ALU in/out
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commitdiff
2020-05-12
Luke Kenneth Casso...
temporary reorg of reg/immediate reading
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commitdiff
2020-05-12
Luke Kenneth Casso...
add 3rd register input to ALUInputData
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commitdiff
2020-05-12
Luke Kenneth Casso...
connect LDSTMulti to 6600 Scoreboard
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commitdiff
2020-05-12
Luke Kenneth Casso...
when doing LD-immediate only acknowledge register 1...
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commitdiff
2020-05-12
Michael Nolan
Add new shift_rot FU for shifts and rotates
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commitdiff
2020-05-12
Michael Nolan
Remove rotates and shifts from alu
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commitdiff
2020-05-11
Michael Nolan
Massively spead up test_pipe_caller.py
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commitdiff
2020-05-11
Michael Nolan
Revert "Greatly speed up test_pipe_caller.py"
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commitdiff
2020-05-11
Michael Nolan
Greatly speed up test_pipe_caller.py
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commitdiff
2020-05-11
Luke Kenneth Casso...
comments from discussion
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commitdiff
2020-05-11
Michael Nolan
Reverse bit order for cr0 in proof
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commitdiff
2020-05-11
Michael Nolan
Check output of cr0 from alu
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commitdiff
2020-05-11
Michael Nolan
Add carry in input to alu testbench
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commitdiff
2020-05-11
Michael Nolan
Add ability to specify initial state for SPRs
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commitdiff
2020-05-11
Michael Nolan
Fix proof_input_stage.py
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commitdiff
2020-05-11
Michael Nolan
Fix rlwimi by reordering the inputs *again*
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commitdiff
2020-05-11
Michael Nolan
Re-enable rlwinm test
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commitdiff
2020-05-11
Michael Nolan
Check write register number too
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commitdiff
2020-05-11
Michael Nolan
Reorder the register reads so the field in read_reg2...
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commitdiff
2020-05-11
Michael Nolan
Have test_pipe_caller actually read from the registers...
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commitdiff
2020-05-11
Michael Nolan
Actually implement rlwimi
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commitdiff
2020-05-11
Luke Kenneth Casso...
comment input signals
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commitdiff
2020-05-11
Luke Kenneth Casso...
cleanup rotator.py
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commitdiff
2020-05-11
Luke Kenneth Casso...
add docstring, missing return module
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commitdiff
2020-05-11
Luke Kenneth Casso...
start cleanup of rotator.py, Cat order is inverted
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commitdiff
2020-05-11
Luke Kenneth Casso...
convert microwatt rotator to nmigen (first draft)
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commitdiff
2020-05-10
Michael Nolan
Add test for rlwnm
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commitdiff
2020-05-10
Michael Nolan
Implement rlwimi as well
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commitdiff
2020-05-10
Michael Nolan
Implement rlwinm in alu
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commitdiff
2020-05-10
Michael Nolan
Add test for rlwinm
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commitdiff
2020-05-10
Michael Nolan
Reduce BMC depth on proof_main_stage.py
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commitdiff
2020-05-10
Luke Kenneth Casso...
use temporary python vars rather than copy signals...
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commitdiff
2020-05-09
Michael Nolan
Add shift left and shift right to main stage proof
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commitdiff
2020-05-09
Luke Kenneth Casso...
sigh ton of syntax errors
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commitdiff
2020-05-09
Luke Kenneth Casso...
bit of reorg, trick on add - put carry in into the LSB
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commitdiff
2020-05-09
Luke Kenneth Casso...
comment output stage
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2020-05-09
Luke Kenneth Casso...
comment maskgen
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2020-05-09
Michael Nolan
Handle algebraic shifts too
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2020-05-09
Michael Nolan
Implement logical shift right
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2020-05-09
Michael Nolan
Add support for sld
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2020-05-09
Michael Nolan
Change shift left to be implemented with rotate and...
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2020-05-09
Michael Nolan
Add mask generator for shift class instructions
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2020-05-09
Michael Nolan
Add shift left opcode to main_stage
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commitdiff
2020-05-09
Michael Nolan
Fix broken mask when x == y
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commitdiff
2020-05-09
Michael Nolan
Add right shift test to test_caller.py
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commitdiff
2020-05-09
Michael Nolan
Add shift test to test_caller, fix fixedshift being...
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commitdiff
2020-05-09
Michael Nolan
Fix helpers.py not playing nicely with selectableInts
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commitdiff
2020-05-09
Michael Nolan
Add reversed add and subtract, as well as lshift and...
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commitdiff
2020-05-09
Luke Kenneth Casso...
comment where ALUIntermediateData to go
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commitdiff
2020-05-09
Luke Kenneth Casso...
TODO on AluIntermediateData
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commitdiff
2020-05-09
Luke Kenneth Casso...
missing sticky-overflow pass-through from middle stage
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commitdiff
2020-05-09
Luke Kenneth Casso...
pass through sticky-overflow
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2020-05-09
Luke Kenneth Casso...
remove unneeded class
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2020-05-09
Luke Kenneth Casso...
clarifying comments
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commitdiff
2020-05-09
Michael Nolan
Minor cleanup
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commitdiff
2020-05-09
Luke Kenneth Casso...
preliminary test for LD/ST "update" mode working
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commitdiff
2020-05-09
Luke Kenneth Casso...
document PowerOp
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2020-05-08
Luke Kenneth Casso...
add comments
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2020-05-08
Luke Kenneth Casso...
add ALUFirstInputData
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commitdiff
2020-05-08
Luke Kenneth Casso...
send address to memory only for one cycle and acknowled...
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commitdiff
2020-05-08
Luke Kenneth Casso...
experimenting
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commitdiff
2020-05-08
Luke Kenneth Casso...
working indexed version of LD/ST CompUnit
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commitdiff
2020-05-08
Luke Kenneth Casso...
hmmm i think LD/ST Comp Unit might actually be working...
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commitdiff
2020-05-08
Michael Nolan
Oops, forgot pipeline.py
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commitdiff
2020-05-08
Michael Nolan
Add tests for immediates, add subf to tests
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commitdiff
2020-05-08
Michael Nolan
Add comments about the purpose of each alu stage
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2020-05-08
Michael Nolan
Add test for alu against simulator
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2020-05-08
Michael Nolan
Add assertions for output stage cr0
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2020-05-08
Michael Nolan
Add output stage
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2020-05-08
Michael Nolan
Add and or and xor to main_stage
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commitdiff
2020-05-08
Michael Nolan
Add carry in and out
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commitdiff
2020-05-08
Michael Nolan
Have input_stage set the b operand to imm_data if it...
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commitdiff
2020-05-08
Michael Nolan
Add extra bits (carry, overflow, etc) to input and...
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commitdiff
2020-05-08
Michael Nolan
Begin adding main ALU stage
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2020-05-08
Michael Nolan
Convert alu to use the op in ctx
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2020-05-08
Michael Nolan
Add FPPipeContext to alu pipe_data
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