soc.git
4 years agomake demo/test ALU look like nmigen pipeline API
Luke Kenneth Casson Leighton [Sat, 23 May 2020 17:08:08 +0000 (18:08 +0100)]
make demo/test ALU look like nmigen pipeline API

4 years agoadd stub DataMerger class
Luke Kenneth Casson Leighton [Sat, 23 May 2020 15:21:21 +0000 (16:21 +0100)]
add stub DataMerger class

4 years agoadd link to regspecs on wiki
Luke Kenneth Casson Leighton [Sat, 23 May 2020 14:57:25 +0000 (15:57 +0100)]
add link to regspecs on wiki

4 years agoadd regspec capability to MultiCompUnit
Luke Kenneth Casson Leighton [Sat, 23 May 2020 14:12:14 +0000 (15:12 +0100)]
add regspec capability to MultiCompUnit

4 years agoModify proof of isel to use full CR register
Michael Nolan [Sat, 23 May 2020 13:24:35 +0000 (09:24 -0400)]
Modify proof of isel to use full CR register

4 years agoAdd test_isel
Michael Nolan [Sat, 23 May 2020 13:16:23 +0000 (09:16 -0400)]
Add test_isel

4 years agomake immediate-or-RA selection optional based on awareness of operation subset
Luke Kenneth Casson Leighton [Sat, 23 May 2020 13:04:06 +0000 (14:04 +0100)]
make immediate-or-RA selection optional based on awareness of operation subset
in MultiCompUnit

4 years agostart to morph MultiCompUnit to take "regspec" as the way to decide the latch and
Luke Kenneth Casson Leighton [Sat, 23 May 2020 12:39:48 +0000 (13:39 +0100)]
start to morph MultiCompUnit to take "regspec" as the way to decide the latch and
oper_i configuration

4 years agoadd CR_ISEL formal proof to CR pipeline
Luke Kenneth Casson Leighton [Sat, 23 May 2020 10:58:43 +0000 (11:58 +0100)]
add CR_ISEL formal proof to CR pipeline

4 years agoadd CR_ISEL (and unit test) to CR pipeline
Luke Kenneth Casson Leighton [Sat, 23 May 2020 10:35:24 +0000 (11:35 +0100)]
add CR_ISEL (and unit test) to CR pipeline

4 years agoupdate to (corrected) csv files for CR_ISEL
Luke Kenneth Casson Leighton [Sat, 23 May 2020 10:20:34 +0000 (11:20 +0100)]
update to (corrected) csv files for CR_ISEL

4 years agoselect bits 2:5 from BC to get CR0 to 7 in DecodeCRin
Luke Kenneth Casson Leighton [Sat, 23 May 2020 03:13:22 +0000 (04:13 +0100)]
select bits 2:5 from BC to get CR0 to 7 in DecodeCRin

4 years agoadd gitignore
Luke Kenneth Casson Leighton [Sat, 23 May 2020 02:19:49 +0000 (03:19 +0100)]
add gitignore

4 years agoCR field on Br input data is specd as 0:3 range
Luke Kenneth Casson Leighton [Sat, 23 May 2020 02:18:10 +0000 (03:18 +0100)]
CR field on Br input data is specd as 0:3 range

4 years agoadd b to CR pipe input data, for isel
Luke Kenneth Casson Leighton [Sat, 23 May 2020 02:15:08 +0000 (03:15 +0100)]
add b to CR pipe input data, for isel

4 years agoadd TODO and link to SHIFT_ROT formal bugreport
Luke Kenneth Casson Leighton [Fri, 22 May 2020 20:37:46 +0000 (21:37 +0100)]
add TODO and link to SHIFT_ROT formal bugreport

4 years agoremove xer.so from ShiftRot formal proof
Luke Kenneth Casson Leighton [Fri, 22 May 2020 20:30:56 +0000 (21:30 +0100)]
remove xer.so from ShiftRot formal proof

4 years agoremove sticky overflow from Shift Rot pipeline
Luke Kenneth Casson Leighton [Fri, 22 May 2020 19:06:41 +0000 (20:06 +0100)]
remove sticky overflow from Shift Rot pipeline

4 years agotest branch ctr ok flag
Luke Kenneth Casson Leighton [Fri, 22 May 2020 18:59:59 +0000 (19:59 +0100)]
test branch ctr ok flag

4 years agocleaner way to test link register ok
Luke Kenneth Casson Leighton [Fri, 22 May 2020 18:52:55 +0000 (19:52 +0100)]
cleaner way to test link register ok

4 years agowhitespace
Luke Kenneth Casson Leighton [Fri, 22 May 2020 18:49:12 +0000 (19:49 +0100)]
whitespace

4 years agoFix link handling in branch proof
Michael Nolan [Fri, 22 May 2020 18:43:32 +0000 (14:43 -0400)]
Fix link handling in branch proof

4 years agoUpdate to latest wiki version - fix cr0 input for OP_CNTZ
Michael Nolan [Fri, 22 May 2020 18:30:58 +0000 (14:30 -0400)]
Update to latest wiki version - fix cr0 input for OP_CNTZ

4 years agovariable-name munging for branch formal
Luke Kenneth Casson Leighton [Fri, 22 May 2020 18:29:26 +0000 (19:29 +0100)]
variable-name munging for branch formal

4 years agoAdd formal proof for branch unit, fix bug with bcreg
Michael Nolan [Fri, 22 May 2020 18:20:13 +0000 (14:20 -0400)]
Add formal proof for branch unit, fix bug with bcreg

4 years agocleanup logical pipe formal proof
Luke Kenneth Casson Leighton [Fri, 22 May 2020 18:20:26 +0000 (19:20 +0100)]
cleanup logical pipe formal proof

4 years agosplit out Logical Input and Output stages to common code, allows removal
Luke Kenneth Casson Leighton [Fri, 22 May 2020 18:19:16 +0000 (19:19 +0100)]
split out Logical Input and Output stages to common code, allows removal
of XER.SO from Logical pipeline

4 years agodiv probably uses ALU not Logical, needs double-checking though
Luke Kenneth Casson Leighton [Fri, 22 May 2020 17:51:08 +0000 (18:51 +0100)]
div probably uses ALU not Logical, needs double-checking though

4 years agoupdate comments for ALUCompUnit
Luke Kenneth Casson Leighton [Fri, 22 May 2020 16:08:15 +0000 (17:08 +0100)]
update comments for ALUCompUnit

4 years agosoc.fu.logical.input_stage no different from ALU: delete
Luke Kenneth Casson Leighton [Fri, 22 May 2020 15:37:15 +0000 (16:37 +0100)]
soc.fu.logical.input_stage no different from ALU: delete

4 years agocovert ALU FU to CommonInputStage
Luke Kenneth Casson Leighton [Fri, 22 May 2020 15:35:32 +0000 (16:35 +0100)]
covert ALU FU to CommonInputStage

4 years agocreate common input pipe spec to avoid code-duplication
Luke Kenneth Casson Leighton [Fri, 22 May 2020 15:32:44 +0000 (16:32 +0100)]
create common input pipe spec to avoid code-duplication

4 years agomove CR over to CompCROpSubset
Luke Kenneth Casson Leighton [Fri, 22 May 2020 15:15:16 +0000 (16:15 +0100)]
move CR over to CompCROpSubset

4 years agoConvert branch unit to new CR interface
Michael Nolan [Fri, 22 May 2020 14:49:26 +0000 (10:49 -0400)]
Convert branch unit to new CR interface

4 years agoComplete CR proof
Michael Nolan [Fri, 22 May 2020 13:31:35 +0000 (09:31 -0400)]
Complete CR proof

4 years agoincrease fu-fu test matrix size
Luke Kenneth Casson Leighton [Fri, 22 May 2020 13:47:37 +0000 (14:47 +0100)]
increase fu-fu test matrix size

4 years agoremove unneeded code
Luke Kenneth Casson Leighton [Fri, 22 May 2020 10:15:17 +0000 (11:15 +0100)]
remove unneeded code

4 years agorename ShiftRot to Mul in fu mul test
Luke Kenneth Casson Leighton [Fri, 22 May 2020 10:14:04 +0000 (11:14 +0100)]
rename ShiftRot to Mul in fu mul test

4 years agorename Logical to Div in fu div test
Luke Kenneth Casson Leighton [Fri, 22 May 2020 10:12:28 +0000 (11:12 +0100)]
rename Logical to Div in fu div test

4 years agocookie-cut start on div pipe
Luke Kenneth Casson Leighton [Fri, 22 May 2020 10:10:35 +0000 (11:10 +0100)]
cookie-cut start on div pipe

4 years agoadd cookie-cut mul pipeline template
Luke Kenneth Casson Leighton [Fri, 22 May 2020 10:03:22 +0000 (11:03 +0100)]
add cookie-cut mul pipeline template

4 years agowhitespace
Luke Kenneth Casson Leighton [Fri, 22 May 2020 09:55:17 +0000 (10:55 +0100)]
whitespace

4 years agoover 80 chars
Luke Kenneth Casson Leighton [Fri, 22 May 2020 09:48:29 +0000 (10:48 +0100)]
over 80 chars

4 years agocomment tidyup
Luke Kenneth Casson Leighton [Fri, 22 May 2020 09:46:45 +0000 (10:46 +0100)]
comment tidyup

4 years agouse CompBROpSubset and reduce it down in size (remove unneeded fields)
Luke Kenneth Casson Leighton [Fri, 22 May 2020 09:34:52 +0000 (10:34 +0100)]
use CompBROpSubset and reduce it down in size (remove unneeded fields)

4 years agocode-shuffle
Luke Kenneth Casson Leighton [Fri, 22 May 2020 09:30:37 +0000 (10:30 +0100)]
code-shuffle

4 years agoremove accidentally added branch input stage
Luke Kenneth Casson Leighton [Fri, 22 May 2020 09:26:27 +0000 (10:26 +0100)]
remove accidentally added branch input stage

4 years agofix ModuleNotFoundError
Tobias Platen [Fri, 22 May 2020 06:38:22 +0000 (08:38 +0200)]
fix ModuleNotFoundError

4 years agoadd fu logical_input_record.py
Luke Kenneth Casson Leighton [Thu, 21 May 2020 20:44:39 +0000 (21:44 +0100)]
add fu logical_input_record.py

4 years agoupdate CROutputData to use Data()
Luke Kenneth Casson Leighton [Thu, 21 May 2020 20:08:10 +0000 (21:08 +0100)]
update CROutputData to use Data()

4 years agoupdate comments
Luke Kenneth Casson Leighton [Thu, 21 May 2020 19:58:26 +0000 (20:58 +0100)]
update comments

4 years agowhitespace cleanup
Luke Kenneth Casson Leighton [Thu, 21 May 2020 19:56:08 +0000 (20:56 +0100)]
whitespace cleanup

4 years agowhitespace cleanup
Luke Kenneth Casson Leighton [Thu, 21 May 2020 19:55:46 +0000 (20:55 +0100)]
whitespace cleanup

4 years agoremove input_cr, output_cr and is_32bit from CompCROpSubset
Luke Kenneth Casson Leighton [Thu, 21 May 2020 19:51:10 +0000 (20:51 +0100)]
remove input_cr, output_cr and is_32bit from CompCROpSubset

4 years agoadd read_cr_whole and write_cr_whole to CompCROpSubset
Luke Kenneth Casson Leighton [Thu, 21 May 2020 19:44:30 +0000 (20:44 +0100)]
add read_cr_whole and write_cr_whole to CompCROpSubset

4 years agoadd first cut at cr_input_record.py
Luke Kenneth Casson Leighton [Thu, 21 May 2020 19:40:54 +0000 (20:40 +0100)]
add first cut at cr_input_record.py

4 years agomove Logical over to use CompLogicalOpSubset
Luke Kenneth Casson Leighton [Thu, 21 May 2020 19:35:33 +0000 (20:35 +0100)]
move Logical over to use CompLogicalOpSubset

4 years agoPartial attempt at proving the new cr unit.
Michael Nolan [Thu, 21 May 2020 19:34:46 +0000 (15:34 -0400)]
Partial attempt at proving the new cr unit.

Shelving for a bit

4 years agoargh syntax error
Luke Kenneth Casson Leighton [Thu, 21 May 2020 19:27:12 +0000 (20:27 +0100)]
argh syntax error

4 years agoupdate and comment CR Input/Output Data specs
Luke Kenneth Casson Leighton [Thu, 21 May 2020 19:26:43 +0000 (20:26 +0100)]
update and comment CR Input/Output Data specs

4 years agoAll CR tests now working
Michael Nolan [Thu, 21 May 2020 19:04:06 +0000 (15:04 -0400)]
All CR tests now working

4 years agoadd CR out decoder debug
Luke Kenneth Casson Leighton [Thu, 21 May 2020 19:01:29 +0000 (20:01 +0100)]
add CR out decoder debug

4 years agoOP_CROP now working
Michael Nolan [Thu, 21 May 2020 18:59:49 +0000 (14:59 -0400)]
OP_CROP now working

4 years agoBegin porting cr pipeline to new interface
Michael Nolan [Thu, 21 May 2020 18:47:52 +0000 (14:47 -0400)]
Begin porting cr pipeline to new interface

4 years agoAdd third cr register select field to decoder
Michael Nolan [Thu, 21 May 2020 18:49:25 +0000 (14:49 -0400)]
Add third cr register select field to decoder

4 years agoUpdate to latest wiki version
Michael Nolan [Thu, 21 May 2020 18:49:14 +0000 (14:49 -0400)]
Update to latest wiki version

4 years agocomment CompALUOpSubset, data_len is actually used by OP_EXTS
Luke Kenneth Casson Leighton [Thu, 21 May 2020 18:41:09 +0000 (19:41 +0100)]
comment CompALUOpSubset, data_len is actually used by OP_EXTS

4 years agocomment DecodeCRIn and DecodeCROut, gratuitously
Luke Kenneth Casson Leighton [Thu, 21 May 2020 18:07:32 +0000 (19:07 +0100)]
comment DecodeCRIn and DecodeCROut, gratuitously

4 years agodocument subkls in CompUnitRecord
Luke Kenneth Casson Leighton [Thu, 21 May 2020 17:57:59 +0000 (18:57 +0100)]
document subkls in CompUnitRecord

4 years agoARSE! frickin git submodules!
Luke Kenneth Casson Leighton [Thu, 21 May 2020 17:54:12 +0000 (18:54 +0100)]
ARSE! frickin git submodules!

4 years agomove CompLDSTOpSubset to fu.ldst.ldst_input_record
Luke Kenneth Casson Leighton [Thu, 21 May 2020 17:52:43 +0000 (18:52 +0100)]
move CompLDSTOpSubset to fu.ldst.ldst_input_record

4 years agoFix broken unit tests in test_caller
Michael Nolan [Thu, 21 May 2020 17:20:01 +0000 (13:20 -0400)]
Fix broken unit tests in test_caller

4 years agoAdd cr output decoder to power_decoder2.py
Michael Nolan [Thu, 21 May 2020 17:13:57 +0000 (13:13 -0400)]
Add cr output decoder to power_decoder2.py

4 years agoAdd CR In decoder to power_decoder2.py
Michael Nolan [Thu, 21 May 2020 16:22:16 +0000 (12:22 -0400)]
Add CR In decoder to power_decoder2.py

4 years agoConvert CR out to enum in power_decoder
Michael Nolan [Thu, 21 May 2020 15:59:54 +0000 (11:59 -0400)]
Convert CR out to enum in power_decoder

4 years agoUpdate to latest wiki version - convert CR out to enum
Michael Nolan [Thu, 21 May 2020 15:59:34 +0000 (11:59 -0400)]
Update to latest wiki version - convert CR out to enum

4 years agoConvert CR In field to enum instead of single bit
Michael Nolan [Thu, 21 May 2020 15:38:04 +0000 (11:38 -0400)]
Convert CR In field to enum instead of single bit

4 years agoUpdate to latest wiki version
Michael Nolan [Thu, 21 May 2020 15:37:54 +0000 (11:37 -0400)]
Update to latest wiki version

4 years agoadd zero_a flag to CompALUOpSubset
Luke Kenneth Casson Leighton [Thu, 21 May 2020 16:48:20 +0000 (17:48 +0100)]
add zero_a flag to CompALUOpSubset

4 years agoadd zero_a flag to Decode2ExecuteType
Luke Kenneth Casson Leighton [Thu, 21 May 2020 16:44:21 +0000 (17:44 +0100)]
add zero_a flag to Decode2ExecuteType

4 years agoFix broken test_adde/add overflow handling to caller.py
Michael Nolan [Thu, 21 May 2020 13:48:44 +0000 (09:48 -0400)]
Fix broken test_adde/add overflow handling to caller.py

4 years agowhitespace/shuffle
Luke Kenneth Casson Leighton [Thu, 21 May 2020 12:02:42 +0000 (13:02 +0100)]
whitespace/shuffle

4 years agomove common functionality between PipeSpecs to soc.fu.pipe_data
Luke Kenneth Casson Leighton [Thu, 21 May 2020 11:57:20 +0000 (12:57 +0100)]
move common functionality between PipeSpecs to soc.fu.pipe_data

4 years agomove FU IntegerData to directory below
Luke Kenneth Casson Leighton [Thu, 21 May 2020 11:45:33 +0000 (12:45 +0100)]
move FU IntegerData to directory below

4 years agobranch output spec nia not cia
Luke Kenneth Casson Leighton [Thu, 21 May 2020 10:43:02 +0000 (11:43 +0100)]
branch output spec nia not cia

4 years agoadd dedicated TrapPipeSpec
Luke Kenneth Casson Leighton [Thu, 21 May 2020 10:42:36 +0000 (11:42 +0100)]
add dedicated TrapPipeSpec

4 years agocreate and use ShiftRotPipeSpec
Luke Kenneth Casson Leighton [Thu, 21 May 2020 10:39:01 +0000 (11:39 +0100)]
create and use ShiftRotPipeSpec

4 years agoconvert to individual PipeSpecs for each pipeline
Luke Kenneth Casson Leighton [Thu, 21 May 2020 10:33:58 +0000 (11:33 +0100)]
convert to individual PipeSpecs for each pipeline

4 years agoadd regspec to ALUPipeSpec
Luke Kenneth Casson Leighton [Thu, 21 May 2020 10:15:25 +0000 (11:15 +0100)]
add regspec to ALUPipeSpec

4 years agouse branch-specific data structures, add "regspecs" to branch pspec
Luke Kenneth Casson Leighton [Thu, 21 May 2020 10:14:52 +0000 (11:14 +0100)]
use branch-specific data structures, add "regspecs" to branch pspec

4 years agocode-morph LDSTCompUnit to use RecordObject structure, like CompUnitALU
Luke Kenneth Casson Leighton [Thu, 21 May 2020 09:50:12 +0000 (10:50 +0100)]
code-morph LDSTCompUnit to use RecordObject structure, like CompUnitALU

4 years agoFixed typo and left-over from refactoring
Cesar Strauss [Thu, 21 May 2020 09:05:57 +0000 (06:05 -0300)]
Fixed typo and left-over from refactoring

4 years agoAdd proof for OP_MCRF
Michael Nolan [Wed, 20 May 2020 20:33:02 +0000 (16:33 -0400)]
Add proof for OP_MCRF

4 years agoAdd proof for OP_MFCR
Michael Nolan [Wed, 20 May 2020 20:21:15 +0000 (16:21 -0400)]
Add proof for OP_MFCR

4 years agoMake test for bpermd exercise the module a bit more
Michael Nolan [Wed, 20 May 2020 19:47:08 +0000 (15:47 -0400)]
Make test for bpermd exercise the module a bit more

4 years agoRevert "*technically* don't use a full crossbar"
Michael Nolan [Wed, 20 May 2020 19:32:36 +0000 (15:32 -0400)]
Revert "*technically* don't use a full crossbar"

This reverts commit e49a0608e702ed60db62fd36ff450828b567db42.
Doesn't reduce logic usage

4 years agoadd link to bugreport in CR pipe formal test
Luke Kenneth Casson Leighton [Wed, 20 May 2020 19:31:32 +0000 (20:31 +0100)]
add link to bugreport in CR pipe formal test

4 years ago*technically* don't use a full crossbar
Michael Nolan [Wed, 20 May 2020 19:29:07 +0000 (15:29 -0400)]
*technically* don't use a full crossbar

4 years agoAdded OP_BPERMD to fu/logical pipeline, with test
colepoirier [Wed, 20 May 2020 19:19:40 +0000 (12:19 -0700)]
Added OP_BPERMD to fu/logical pipeline, with test

4 years agoRevert "assign index to temporary"
Michael Nolan [Wed, 20 May 2020 19:17:55 +0000 (15:17 -0400)]
Revert "assign index to temporary"

This reverts commit e0e859f73a3e38365f8a5fef20628d6a0aae4c1f.