Eric Engestrom [Tue, 30 Jul 2019 15:17:15 +0000 (16:17 +0100)]
travis: drop unnecessary Meson option for MacOS
Those are already their default values on MacOS.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Jason Ekstrand [Sat, 20 Jul 2019 13:17:59 +0000 (08:17 -0500)]
intel/vec4: Drop all of the 64-bit varying code
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 19 Jul 2019 22:38:04 +0000 (17:38 -0500)]
intel/fs: Drop all of the 64-bit varying code
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 19 Jul 2019 22:23:26 +0000 (17:23 -0500)]
intel: Use NIR to lower 64-bit varying access
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Fri, 19 Jul 2019 22:10:07 +0000 (17:10 -0500)]
nir/lower_io: Add an option to lower 64-bit varyings
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jorge Natz [Wed, 31 Jul 2019 22:50:43 +0000 (22:50 +0000)]
docs: Update Platforms and Drivers page with more comprehensive information.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Dave Airlie [Wed, 31 Jul 2019 04:05:49 +0000 (14:05 +1000)]
nir: use common deref has indirect code in scratch lowering.
This doesn't seem to need it's own copy here.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Eric Engestrom [Wed, 31 Jul 2019 21:50:56 +0000 (22:50 +0100)]
nir: remove explicit nir_intrinsic_index_flag values
These were left after a rebase and happen to make
NIR_INTRINSIC_SWIZZLE_MASK == NIR_INTRINSIC_SRC_ACCESS, which is how it
was noticed.
Fixes: 6f20643b471a851c936f ("nir: Allow qualifiers on copy_deref and image instructions")
Cc: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Yevhenii Kolesnikov [Fri, 26 Jul 2019 14:30:55 +0000 (17:30 +0300)]
state_tracker: Free Labels for querry and tranform_feedback
Memory leaks were observed on iris with GL_KHR_debug.
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Kenneth Graunke [Sat, 16 Feb 2019 08:57:54 +0000 (00:57 -0800)]
iris: Skip emitting 3DSTATE_INDEX_BUFFER if possible
We were emitting 3DSTATE_INDEX_BUFFER on every indexed draw, even if
back-to-back draws referred to the same index buffer. This improves
drawoverhead scores in the DrawElements cases by about 10%, by giving
us even more minimal batches.
Mike Blumenkrantz [Thu, 6 Jun 2019 23:47:23 +0000 (19:47 -0400)]
st/dri: simplify dri_get_egl_image by reusing dri2_format_table
this makes dri2_get_mapping_by_fourcc accessible from dri_helpers.h
and does a direct lookup on the fourcc id to match the pipe format
v2 (Ken): Allow map to be NULL, use img->texture->format.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Erico Nunes [Thu, 18 Jul 2019 19:13:19 +0000 (21:13 +0200)]
lima: enable lower_bitops in ppir
The mali pp doesn't support integers and some nir_algebraic
optimizations may result in ops that are not easily lowerable to floats,
so disable optimizations resulting in bitops.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Erico Nunes [Thu, 18 Jul 2019 18:56:27 +0000 (20:56 +0200)]
nir/algebraic: rename lower_bitshift to lower_bitops
Optimizations that insert bitshift or bitwise operations should not be
applied on GPUs that don't support integer operations.
The .lower_bitshift could be used to control the bitshift related ones,
but there was also one bitwise optimization uncovered.
Since only lima and freedreno use this option and the use case is that
no bit operations are wanted, let's rename it to .lower_bitops and use
it to control all bitops related optimizations.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Erico Nunes [Sat, 27 Jul 2019 16:10:46 +0000 (18:10 +0200)]
lima/ppir: lower fdot in nir_opt_algebraic
Now that we have fsum in nir, we can move fdot lowering there.
This helps reduce ppir complexity and enables the lowered ops to be part
of other nir optimizations in the optimization loop.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Erico Nunes [Sat, 27 Jul 2019 15:58:53 +0000 (17:58 +0200)]
nir/algebraic: add new fsum ops and fdot lowering
The Mali400 pp doesn't implement fdot but has fsum3 and fsum4, which can
be used to optimize fdot lowering. fsum2 is not implemented and can be
further lowered to an add with the vector components.
Currently lima ppir handles this lowering internally, however this
happens in a very late stage and requires a big chunk of code compared
to a nir_opt_algebraic lowering.
By having fsum in nir, we can reduce ppir complexity and enable the
lowered ops to be part of other nir optimizations in the optimization
loop.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Erico Nunes [Sun, 28 Jul 2019 19:27:46 +0000 (21:27 +0200)]
lima/ppir: refactor texture code to simplify scheduler
The 'varying fetch' pp instruction deals only with coordinates, and
'texture fetch' deals only with the sampler index.
Previously it was not possible to clearly map ppir_op_load_coords and
ppir_op_load_texture to pp instructions as the source coordinates were
kept in the ppir_op_load_texture node, making this harder to maintain.
The refactor is made with the attempt to clearly map ppir_op_load_coords
to the 'varying fetch' and ppir_op_load_texture to the 'texture fetch'.
The coordinates are still temporarily kept in the ppir_op_load_texture
node as nir has both sampler and coordinates in a single instruction and
it is only possible to output one ppir node during emit. But now after
lowering, the sources are transferred to the (always) created
ppir_op_load_coords node, and it should be possible to directly map them
to their pp instructions from there onwards.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Erico Nunes [Sun, 28 Jul 2019 19:25:42 +0000 (21:25 +0200)]
lima/ppir: lower texture projection
Lower texture projection in ppir using nir_lower_tex and nir_lower_tex.
This will insert a mul with the coordinate division before the load
varying.
Even though the lima pp supports projection in the load varying
instruction while loading the coordinates (from a register or a
varying), it requires that both the coordinates and projector be
components in a single register.
nir currently handles them in separate ssa, and attempting to merge them
manually may end up in worse code than just doing the coordinate
division manually. So for now let's just lower the projection to add
support for it in lima.
In the future, an optimization pass may be implemented in lima to ensure
that both coords and projector come in the same register, then this
lowering may be disabled and in this case lima may use the built-in
projection and save the mul instruction from lowering.
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Vinson Lee [Wed, 31 Jul 2019 02:24:16 +0000 (19:24 -0700)]
scons: Fix random_r check.
Fixes: 597bddad47e8 ("scons: Test for random_r()")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Wed, 31 Jul 2019 18:05:49 +0000 (11:05 -0700)]
Revert "st/dri: simplify dri_get_egl_image by reusing dri2_format_table"
This reverts commit
c47af8b95f26bd83efe322ff0baa52263fb8625e. It causes
dEQP-EGL regressions. (I think there is an easy fix, but we'll have it
go through review again.)
Alyssa Rosenzweig [Tue, 30 Jul 2019 19:25:21 +0000 (12:25 -0700)]
pan/midgard: Don't special case inline_constant
Another constant source of bugs. Ain't that special.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 30 Jul 2019 19:20:24 +0000 (12:20 -0700)]
pan/midgard: De-special-case branching
It's not that special.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 31 Jul 2019 16:08:07 +0000 (09:08 -0700)]
panfrost: Add MALI_SAMP_NORM_COORDS flag
Corresponds to the normalized coordinates? flag on images in OpenCL and
evidently also shows up in GL, so let's wire it in.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 31 Jul 2019 15:50:02 +0000 (08:50 -0700)]
panfrost: Simplify filter_mode definition
It's just a bit field containing some flags; there's no need for all the
macro magic.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 31 Jul 2019 14:25:24 +0000 (07:25 -0700)]
pan/midgard: Shrink "compute FBD"
We still don't know what it is, but from a newer trace we now know it's
half the size we thought it was.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 31 Jul 2019 14:20:29 +0000 (07:20 -0700)]
panfrost: Flip texture/sampler fields
We had them backwards in both the command stream and the Midgard stack.
In OpenGL ES 2.0, they're always the same, but in Vulkan/later-GL/CL
they diverge so we can fix this.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Wed, 31 Jul 2019 00:27:03 +0000 (17:27 -0700)]
panfrost: Add MALI_ATTR_IMAGE value
Images are implemented (in part) as special attributes, so include
support for decoding this.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Mike Blumenkrantz [Thu, 6 Jun 2019 23:47:23 +0000 (19:47 -0400)]
st/dri: simplify dri_get_egl_image by reusing dri2_format_table
this makes dri2_get_mapping_by_fourcc accessible from dri_helpers.h
and does a direct lookup on the fourcc id to match the pipe format
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Mike Blumenkrantz [Wed, 29 May 2019 21:14:32 +0000 (17:14 -0400)]
gallium: add handling for YUV planar surfaces
st/dri:
this adds a table (similar to the one in i965) which provides
mappings for turning various planar formats into multiple sampler views.
whereas only NV12 and IYUV were supported, now many more formats are
supported here:
* P0XX
* YUV4XX
* YVU4XX
* AYUV
* XYUV
* YUYV
* UYVY
the table is used directly to handle image creation, simplifying
a lot of code and resolving related TODO/FIXME items where workarounds were
previously in place to manage NV12 and IYUV formats exclusively
st/mesa:
the changes here relate to setting up samplers for the planar formats.
this requires:
* checking for driver support for all the sampler formats
* creating the samplers with the corresponding formats and swizzling
* running nir_lower_tex with the appropriate options to trigger the lowering
for each plane->sampler
fixes kwg/mesa#36
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Mike Blumenkrantz [Wed, 3 Jul 2019 16:14:54 +0000 (12:14 -0400)]
gallium: add AYUV and XYUV formats
this only adds the PIPE_FORMAT members, not any direct handling for them
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Alyssa Rosenzweig [Wed, 31 Jul 2019 00:07:25 +0000 (17:07 -0700)]
pan/midgard: Simplify discard logic
The "branch offset" is, in fact, ignored.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 30 Jul 2019 23:55:16 +0000 (16:55 -0700)]
pan/midgard: Add units for more instructions
For everything but freduce, we have some sense of what units the
instruction takes.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Tue, 30 Jul 2019 23:46:57 +0000 (16:46 -0700)]
pan/midgard: Fix ball/bany opcode table
This were seriously messed up beyond all recognition. How we're passing
shaders.random.* is a mystery.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Alyssa Rosenzweig [Mon, 29 Jul 2019 16:15:32 +0000 (09:15 -0700)]
pan/midgard: Document branch combination LUT
This took way longer to figure out than it should have..
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Kenneth Graunke [Wed, 31 Jul 2019 01:07:17 +0000 (18:07 -0700)]
st/mesa: Skip scissor rect updates when scissor is entirely disabled.
If any scissor rectangles are enabled, then we need to set proper
scissor rectangles for all viewports. But if the scissor test is
entirely disabled, then we can skip updating any scissor rectangles.
Without this step, we were updating the scissor rectangles based on
the current framebuffer size. So if an app rendered to a variety of
render targets at different sizes, with scissor test disabled each
time, we'd still be continually updating the scissor rectangles,
even though it's not necessary.
In Civilization VI, this drops us from 310-350 set_scissor_state
calls per frame to 0, as it doesn't appear to use scissor testing.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Emil Velikov [Fri, 5 Jul 2019 10:14:30 +0000 (11:14 +0100)]
egl/drm: ensure the backing gbm is set before using it
Currently, if we error out before gbm_dri is set (say due to a different
name of the backing GBM implementation, or otherwise) the tear down will
trigger a NULL ptr deref and crash out.
Move the gbm_dri initialization as early as possible.
v2: Drop check in dri2_teardowm_drm (Eric)
Reported-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Eric Engestrom [Mon, 29 Jul 2019 23:44:21 +0000 (00:44 +0100)]
docs: update required meson version
Fixes: f7b6a8d12fdc446e3251 ("meson: bump required version to 0.46")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Samuel Pitoiset [Wed, 31 Jul 2019 07:39:23 +0000 (09:39 +0200)]
radv/gfx10: implement a GE bug workaround
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 31 Jul 2019 07:39:22 +0000 (09:39 +0200)]
radv/gfx10: remove an obsolete VGT_REUSE_OFF workaround
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 31 Jul 2019 07:39:21 +0000 (09:39 +0200)]
radv/gfx10: disable LATE_ALLOC_GS on Navi14
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 31 Jul 2019 07:39:20 +0000 (09:39 +0200)]
radv/gfx10: implement a bug workaround for GE_PC_ALLOC
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 31 Jul 2019 07:39:19 +0000 (09:39 +0200)]
radv/gfx10: implement a bug workaround for NGG -> legacy transitions
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Samuel Pitoiset [Wed, 31 Jul 2019 07:39:18 +0000 (09:39 +0200)]
radv: skip draw calls with 0-sized index buffers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Eric Engestrom [Tue, 30 Jul 2019 21:05:22 +0000 (22:05 +0100)]
autotools: delete leftover script wrapper
Randomly came across this file, which was likely only used by autotools
to pass arguments to the test.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Engestrom [Sat, 22 Jun 2019 18:40:04 +0000 (19:40 +0100)]
virgl: make use of local variable
Otherwise that variable is only used in an assert() and would need an
ASSERTED to avoid the warning.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 18:39:09 +0000 (19:39 +0100)]
mesa: add an ASSERTED
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 18:38:17 +0000 (19:38 +0100)]
compiler/nir: add an ASSERTED
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 18:37:53 +0000 (19:37 +0100)]
intel: add a couple of ASSERTED
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Wed, 19 Jun 2019 11:47:19 +0000 (12:47 +0100)]
tree-wide: replace MAYBE_UNUSED with ASSERTED
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Thu, 4 Jul 2019 13:28:10 +0000 (14:28 +0100)]
r600: replace MAYBE_UNUSED with specific #ifdef
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 17:08:08 +0000 (18:08 +0100)]
gallium/aux: replace MAYBE_UNUSED with UNUSED
MAYBE_UNUSED is going away, so let's replace legitimate uses of it with
UNUSED, which the former aliased to so far anyway.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 17:05:14 +0000 (18:05 +0100)]
mesa: replace MAYBE_UNUSED with UNUSED
MAYBE_UNUSED is going away, so let's replace legitimate uses of it with
UNUSED, which the former aliased to so far anyway.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 14:29:52 +0000 (15:29 +0100)]
v3d: replace MAYBE_UNUSED with UNUSED
MAYBE_UNUSED is going away, so let's replace legitimate uses of it with
UNUSED, which the former aliased to so far anyway.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 14:29:03 +0000 (15:29 +0100)]
v3d: drop incorrect MAYBE_UNUSED
While at it, use that `screen` variable everywhere.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Tue, 30 Jul 2019 14:11:23 +0000 (15:11 +0100)]
st/tests: drop incorrect MAYBE_UNUSED
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 14:19:12 +0000 (15:19 +0100)]
radv: drop incorrect MAYBE_UNUSED
`compressed` is clearly always used on the line right after.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 14:16:23 +0000 (15:16 +0100)]
r600: move variable to proper scope
It helps show when it's actually used.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 14:21:44 +0000 (15:21 +0100)]
compiler: replace MAYBE_UNUSED with UNUSED
MAYBE_UNUSED is going away, so let's replace legitimate uses of it with
UNUSED, which the former aliased to so far anyway.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 17:18:40 +0000 (18:18 +0100)]
mesa: drop MAYBE_UNUSED var
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 17:07:02 +0000 (18:07 +0100)]
anv: drop MAYBE_UNUSED var
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 17:11:44 +0000 (18:11 +0100)]
i965: drop unused MAYBE_UNUSED function
Added in
1b85c605a60a80975460 but never used.
Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 17:11:04 +0000 (18:11 +0100)]
i965: replace MAYBE_UNUSED with GEN condition
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 12:31:53 +0000 (13:31 +0100)]
intel: replace MAYBE_UNUSED with UNUSED
MAYBE_UNUSED is going away, so let's replace legitimate uses of it with
UNUSED, which the former aliased to so far anyway.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 17:02:52 +0000 (18:02 +0100)]
intel: drop incorrect MAYBE_UNUSED
All these are actually always used.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Sat, 22 Jun 2019 13:27:29 +0000 (14:27 +0100)]
egl: replace MAYBE_UNUSED with UNUSED
MAYBE_UNUSED is going away, so let's replace legitimate uses of it with
UNUSED, which the former aliased to so far anyway.
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Samuel Pitoiset [Tue, 30 Jul 2019 16:32:42 +0000 (18:32 +0200)]
radv/gfx10: add Wave32 support for compute shaders
It can be enabled with RADV_PERFTEST=cswave32.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Kenneth Graunke [Wed, 31 Jul 2019 01:49:47 +0000 (18:49 -0700)]
iris: Skip repeated depth buffer disables.
Often times, the depth buffer is entirely disabled, but color render
targets change. For example, GenerateMipmaps will change the color
render target for each miplevel, but there is no depth buffer.
In the Civilization VI benchmark, this drops the median number of
3DSTATE_DEPTH_BUFFER etc. packets emitted per frame from 472 to 34.
Marek Olšák [Thu, 25 Jul 2019 01:49:36 +0000 (21:49 -0400)]
radeonsi: release NIR in the right place to fix crashes
Marek Olšák [Thu, 25 Jul 2019 00:07:52 +0000 (20:07 -0400)]
radeonsi: fix packing of key.mono.u.ps
Marek Olšák [Thu, 25 Jul 2019 00:21:27 +0000 (20:21 -0400)]
ac/nir: fix incorrect Phis if callbacks use control flow inside control flow
Marek Olšák [Wed, 24 Jul 2019 21:44:51 +0000 (17:44 -0400)]
ac/nir: handle abs modifier
Marek Olšák [Wed, 24 Jul 2019 21:36:25 +0000 (17:36 -0400)]
ac: fix a memory leak in the error path of ac_build_type_name_for_intr
Marek Olšák [Wed, 24 Jul 2019 21:19:38 +0000 (17:19 -0400)]
ac: allow control flow statements in NIR callbacks
This fixes a crash when compiling geometry shaders on radeonsi.
Marek Olšák [Wed, 24 Jul 2019 03:11:40 +0000 (23:11 -0400)]
ac/nir: handle negate modifier
Marek Olšák [Wed, 24 Jul 2019 00:49:27 +0000 (20:49 -0400)]
radeonsi: don't use lp_build_if for the prim discard compute shader
Marek Olšák [Wed, 24 Jul 2019 00:34:03 +0000 (20:34 -0400)]
radeonsi: don't use lp_build_if for the wrapping if block in the VS prolog
Marek Olšák [Wed, 24 Jul 2019 00:34:03 +0000 (20:34 -0400)]
radeonsi: don't use lp_build_if for the wrapping if block in merged shaders
Marek Olšák [Wed, 24 Jul 2019 00:41:55 +0000 (20:41 -0400)]
radeonsi: don't use lp_build_if (in most common places)
Marek Olšák [Wed, 24 Jul 2019 00:41:30 +0000 (20:41 -0400)]
radeonsi: don't use lp_build_alloca
Marek Olšák [Tue, 23 Jul 2019 23:32:50 +0000 (19:32 -0400)]
radeonsi/nir: implement FBFETCH for KHR_blend_equation_advanced
Marek Olšák [Tue, 23 Jul 2019 23:22:57 +0000 (19:22 -0400)]
radeonsi/nir: set input_interpolate_loc for color inputs
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Marek Olšák [Tue, 23 Jul 2019 23:15:45 +0000 (19:15 -0400)]
radeonsi/nir: set tgsi_shader_info::num_memory_instructions
Marek Olšák [Tue, 23 Jul 2019 23:12:45 +0000 (19:12 -0400)]
radeonsi/nir: accurately set input_usage_mask for doubles (v2)
v2: fix doubles
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Tue, 23 Jul 2019 22:55:47 +0000 (18:55 -0400)]
radeonsi/nir: accurately set output_usagemask (v2)
v2: fix doubles
Marek Olšák [Tue, 23 Jul 2019 22:03:39 +0000 (18:03 -0400)]
radeonsi/nir: accurately set reads_*_outputs for TCS
Marek Olšák [Tue, 23 Jul 2019 22:00:50 +0000 (18:00 -0400)]
radeonsi/nir: clean up gather_intrinsic_load_deref_input_info
Marek Olšák [Tue, 23 Jul 2019 21:36:09 +0000 (17:36 -0400)]
radeonsi/nir: add an option to convert TGSI to NIR
Use at your own risk.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Tue, 23 Jul 2019 21:42:26 +0000 (17:42 -0400)]
radeonsi/nir: clean up some nir_scan_shader code
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Tue, 23 Jul 2019 21:46:38 +0000 (17:46 -0400)]
radeonsi/gfx10: disable DCC image stores
Uncompressed image stores are usually faster.
Also, the driver didn't set WRITE_COMPRESS_ENABLE, so I don't know
what the hw did for image stores.
Marek Olšák [Tue, 23 Jul 2019 04:32:06 +0000 (00:32 -0400)]
radeonsi: adjust RB+ blend optimization settings
based on PAL
Marek Olšák [Tue, 23 Jul 2019 05:55:12 +0000 (01:55 -0400)]
ac/surface: allow linear swizzle mode automatic selection on gfx9 & 10
let addrlib make the decision to get the same result as PAL.
Pierre-Eric Pelloux-Prayer [Thu, 2 May 2019 13:01:05 +0000 (15:01 +0200)]
mesa: add EXT_dsa indexed generic queries
Only GetPointerIndexedvEXT needs an implementation, the other functions are
aliases of existing functions.
Pierre-Eric Pelloux-Prayer [Mon, 29 Apr 2019 15:39:49 +0000 (17:39 +0200)]
mesa: add EXT_dsa indexed texture commands functions
Added functions:
- EnableClientStateIndexedEXT
- DisableClientStateIndexedEXT
- EnableClientStateiEXT
- DisableClientStateiEXT
Implemented using the idiom provided by the spec:
if (array == TEXTURE_COORD_ARRAY) {
int savedClientActiveTexture;
GetIntegerv(CLIENT_ACTIVE_TEXTURE, &savedClientActiveTexture);
ClientActiveTexture(TEXTURE0+index);
XXX(array);
ClientActiveTexture(savedActiveTexture);
} else {
// Invalid enum
}
Pierre-Eric Pelloux-Prayer [Mon, 29 Apr 2019 11:53:29 +0000 (13:53 +0200)]
mesa: add EXT_dsa (Named)Framebuffer functions
These functions dont support display list as specified:
Should the selector-free versions of various OpenGL 3.0 and
EXT_framebuffer_object framebuffer object commands not be allowed
in display lists [...]?
RESOLVED: Yes
Pierre-Eric Pelloux-Prayer [Fri, 26 Apr 2019 16:10:44 +0000 (18:10 +0200)]
mesa: add EXT_dsa NamedBuffer functions
Jason Ekstrand [Tue, 30 Jul 2019 23:07:08 +0000 (18:07 -0500)]
i965/curbe: Look at SYSTEM_VALUE_FRAG_COORD instead of VARYING_SLOT_POS
When transitioning gl_FragCoord over to a system value, we missed one
instance of VARYING_SLOT_POS in i965. As of this commit, i965 has no
references to VARYING_SLOT_POS.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111263
Fixes: 4bb6e6817ec "intel: Use a system value for gl_FragCoord"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Fri, 26 Jul 2019 21:03:08 +0000 (16:03 -0500)]
intel/fs: Implement quad_swap_horizontal with a swizzle on gen7
This fixes dEQP-VK.subgroups.quad.compute.subgroupquadswaphorizontal_*
on all gen7 platforms.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Thu, 25 Jul 2019 23:28:44 +0000 (18:28 -0500)]
intel/fs: Use ALIGN16 instructions for all derivatives on gen <= 7
The issue here was discovered by a set of Vulkan CTS tests:
dEQP-VK.glsl.derivate.*.dynamic_*
These tests use ballot ops to construct a branch condition that takes
the same path for each 2x2 quad but may not be uniform across the whole
subgroup. They then tests that derivatives work and give the correct
value even when executed inside such a branch. Because the derivative
isn't executed in uniform control-flow and the values coming into the
derivative aren't smooth (or worse, linear), they nicely catch bugs that
aren't uncovered by simpler derivative tests.
Unfortunately, these tests require Vulkan and the equivalent GL test
would require the GL_ARB_shader_ballot extension which requires int64.
Because the requirements for these tests are so high, it's not easy to
test on older hardware and the bug is only proven to exist on gen7;
gen4-6 are a conjecture.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Tue, 30 Jul 2019 14:41:06 +0000 (15:41 +0100)]
scons+meson: suppress spammy build warning on MacOS
Originally introduced in
c7f36574506838274460 ("darwin: Suppress type
conversion warnings for GLhandleARB") to fix Bugzilla #66346 [1], this
workaround was never ported to Scons or Meson.
[1] https://bugs.freedesktop.org/66346
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Matt Turner [Mon, 17 Oct 2016 21:12:28 +0000 (14:12 -0700)]
i965/fs: Print the scheduler mode.
Line wrap some awfully long lines while we are here.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Matt Turner [Mon, 17 Oct 2016 21:10:26 +0000 (14:10 -0700)]
i965/fs: Add a shader_stats struct.
It'll grow further, and we'd like to avoid adding an additional
parameter to fs_generator() for each new piece of data.
v2 (idr): Rebase on 17 months. Track a visitor instead of a cfg.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>