soc.git
4 years agofix broken remainder for div FSM
Jacob Lifshay [Tue, 25 Aug 2020 18:54:51 +0000 (11:54 -0700)]
fix broken remainder for div FSM

4 years agoclean up formatting
Jacob Lifshay [Tue, 25 Aug 2020 18:16:03 +0000 (11:16 -0700)]
clean up formatting

4 years agoalthough shift-rot does not alter XER.so it still needs it as input for CR0
Luke Kenneth Casson Leighton [Tue, 25 Aug 2020 13:30:04 +0000 (14:30 +0100)]
although shift-rot does not alter XER.so it still needs it as input for CR0

4 years agoadd way to capture CR from DMI in litex sim
Luke Kenneth Casson Leighton [Tue, 25 Aug 2020 11:59:38 +0000 (12:59 +0100)]
add way to capture CR from DMI in litex sim

4 years agoadd CR read to DMI interface
Luke Kenneth Casson Leighton [Tue, 25 Aug 2020 11:26:19 +0000 (12:26 +0100)]
add CR read to DMI interface

4 years agoshorten using temp vars
Luke Kenneth Casson Leighton [Tue, 25 Aug 2020 10:56:36 +0000 (11:56 +0100)]
shorten using temp vars

4 years agoadd CR DMI interface
Luke Kenneth Casson Leighton [Tue, 25 Aug 2020 10:54:35 +0000 (11:54 +0100)]
add CR DMI interface

4 years agoadd crxor unit test to qemu
Luke Kenneth Casson Leighton [Tue, 25 Aug 2020 10:52:24 +0000 (11:52 +0100)]
add crxor unit test to qemu

4 years agodcache.py fix whitespace, fomatting, syntax
Cole Poirier [Tue, 25 Aug 2020 01:19:24 +0000 (18:19 -0700)]
dcache.py fix whitespace, fomatting, syntax

4 years agodcache.py fix formatting
Cole Poirier [Tue, 25 Aug 2020 01:03:14 +0000 (18:03 -0700)]
dcache.py fix formatting

4 years agodcache.py move Reservation RecordObject to top of file
Cole Poirier [Tue, 25 Aug 2020 01:01:36 +0000 (18:01 -0700)]
dcache.py move Reservation RecordObject to top of file

4 years agodcache.py move RegStage1 RecordObject to top of file
Cole Poirier [Tue, 25 Aug 2020 00:59:16 +0000 (17:59 -0700)]
dcache.py move RegStage1 RecordObject to top of file

4 years agodcache.py move MemAccessRequest RecordObject to top of file, small
Cole Poirier [Tue, 25 Aug 2020 00:47:41 +0000 (17:47 -0700)]
dcache.py move MemAccessRequest RecordObject to top of file, small
formatting changes

4 years agodcache.py move Stage0 RecordObject to top of file
Cole Poirier [Tue, 25 Aug 2020 00:40:19 +0000 (17:40 -0700)]
dcache.py move Stage0 RecordObject to top of file

4 years agoargh, reading regfile over DMI was overlapped and corrupting reg 0
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 22:27:02 +0000 (23:27 +0100)]
argh, reading regfile over DMI was overlapped and corrupting reg 0

4 years agoadd isel CR tests to run on qemu (confirmed working)
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 18:45:13 +0000 (19:45 +0100)]
add isel CR tests to run on qemu (confirmed working)

4 years agoTestCachedMemoryPortInterface cleanup
Tobias Platen [Mon, 24 Aug 2020 16:50:47 +0000 (18:50 +0200)]
TestCachedMemoryPortInterface cleanup

4 years agomake it easier to select FSM/Pipe DIV unit
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 14:32:02 +0000 (15:32 +0100)]
make it easier to select FSM/Pipe DIV unit

4 years agofix *another* ld-update-related timing / FSM issue
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 14:04:55 +0000 (15:04 +0100)]
fix *another* ld-update-related timing / FSM issue

4 years agotidyup / shuffle after review
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 12:42:03 +0000 (13:42 +0100)]
tidyup / shuffle after review

4 years agoremove default parameter
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 12:30:28 +0000 (13:30 +0100)]
remove default parameter

4 years ago"WAY" does not exist - range(NUM_WAYS) was intended
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 11:43:34 +0000 (12:43 +0100)]
"WAY" does not exist - range(NUM_WAYS) was intended

4 years agouse WAY_BITS in appropriate locations
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 11:37:32 +0000 (12:37 +0100)]
use WAY_BITS in appropriate locations

4 years agoreminder that the license (reflecting what is in setup.py) is the LGPLv3
Luke Kenneth Casson Leighton [Mon, 24 Aug 2020 11:18:04 +0000 (12:18 +0100)]
reminder that the license (reflecting what is in setup.py) is the LGPLv3

4 years agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Mon, 24 Aug 2020 00:48:16 +0000 (17:48 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

4 years agodcache.py commit first full tranlation pass, about five percent left
Cole Poirier [Mon, 24 Aug 2020 00:46:21 +0000 (17:46 -0700)]
dcache.py commit first full tranlation pass, about five percent left
undone as I don't understand how to do it and need help

4 years agoupdate copyright notices to include additional primary author
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 21:07:33 +0000 (22:07 +0100)]
update copyright notices to include additional primary author
(michael, please make sure to be properly informed on copyright law.
the git commit logs are the "ultimate" record, and simply being just one
of the authors does not mean that you can take the entire code and re-license
it under your own license.  you can only take the portions that *you* wrote)

4 years agoadd load algebraic immediate unit test
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 20:57:10 +0000 (21:57 +0100)]
add load algebraic immediate unit test

4 years agoadd algebraic ld tests lwax, lwaux
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 20:39:25 +0000 (21:39 +0100)]
add algebraic ld tests lwax, lwaux

4 years agoAdd copyright to files I primarily authored in simulator/
Michael Nolan [Sun, 23 Aug 2020 20:06:24 +0000 (16:06 -0400)]
Add copyright to files I primarily authored in simulator/

4 years agoAdd copyright to files in fu/ that I was the primary author on
Michael Nolan [Sun, 23 Aug 2020 20:04:13 +0000 (16:04 -0400)]
Add copyright to files in fu/ that I was the primary author on

4 years agoAdd copyright statement to power_decoder.py
Michael Nolan [Sun, 23 Aug 2020 19:51:32 +0000 (15:51 -0400)]
Add copyright statement to power_decoder.py

Michael Copyright

4 years agobring "core stopped" signal out through DMI interface
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 19:49:13 +0000 (20:49 +0100)]
bring "core stopped" signal out through DMI interface

4 years agoadd in DMI "stat" loop which monitors core "stopping"
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 19:36:58 +0000 (20:36 +0100)]
add in DMI "stat" loop which monitors core "stopping"

4 years agoAllow an empty style, and passing default styles as arguments
Cesar Strauss [Sun, 23 Aug 2020 19:26:20 +0000 (16:26 -0300)]
Allow an empty style, and passing default styles as arguments

This permits to entirely avoid passing a style structure, if only
the root selector is needed.

4 years agoAdd comment node type
Cesar Strauss [Sun, 23 Aug 2020 18:31:12 +0000 (15:31 -0300)]
Add comment node type

4 years agoAdd base and display styles
Cesar Strauss [Sun, 23 Aug 2020 18:06:21 +0000 (15:06 -0300)]
Add base and display styles

4 years agoApply style from node own name
Cesar Strauss [Sun, 23 Aug 2020 17:51:35 +0000 (14:51 -0300)]
Apply style from node own name

4 years agoAdd color style
Cesar Strauss [Sun, 23 Aug 2020 17:44:54 +0000 (14:44 -0300)]
Add color style

4 years agoCollect styles from the tuple
Cesar Strauss [Sun, 23 Aug 2020 17:14:52 +0000 (14:14 -0300)]
Collect styles from the tuple

4 years agoPropagate the root style to all signals
Cesar Strauss [Sun, 23 Aug 2020 16:17:24 +0000 (13:17 -0300)]
Propagate the root style to all signals

Begin by prepending the default module path to all signal names.

4 years agocomment why litex sim mem map is altered
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 14:18:54 +0000 (15:18 +0100)]
comment why litex sim mem map is altered

4 years agomultiply does not have invert_in, zero_a or invert_out
Luke Kenneth Casson Leighton [Sun, 23 Aug 2020 11:32:10 +0000 (12:32 +0100)]
multiply does not have invert_in, zero_a or invert_out

4 years agorename invert_a to invert_in because logical inverts RB
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 23:53:25 +0000 (00:53 +0100)]
rename invert_a to invert_in because logical inverts RB

4 years agoupdate submodule
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 23:46:13 +0000 (00:46 +0100)]
update submodule

4 years agoload bios not 1.bin unit test
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 23:46:00 +0000 (00:46 +0100)]
load bios not 1.bin unit test

4 years agoadd extra div regression tests
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 23:45:28 +0000 (00:45 +0100)]
add extra div regression tests

4 years agoMove comments to the docstring
Cesar Strauss [Sat, 22 Aug 2020 21:13:51 +0000 (18:13 -0300)]
Move comments to the docstring

4 years agoWalk the DOM and emit the trace names
Cesar Strauss [Sat, 22 Aug 2020 19:14:53 +0000 (16:14 -0300)]
Walk the DOM and emit the trace names

Descend into the children of each group, while emitting the group
delimiters.

4 years agoadd eqv to logical unit test
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 15:10:03 +0000 (16:10 +0100)]
add eqv to logical unit test

4 years agoadd nor and nand to unit test
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 15:09:06 +0000 (16:09 +0100)]
add nor and nand to unit test

4 years agomoved to div pipe temporarily in compunits
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 15:07:22 +0000 (16:07 +0100)]
moved to div pipe temporarily in compunits

4 years agobug in andc and orc, complement was taking place on RA not RB
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 14:39:29 +0000 (15:39 +0100)]
bug in andc and orc, complement was taking place on RA not RB

4 years agoextend addis test
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 14:11:46 +0000 (15:11 +0100)]
extend addis test

4 years agoadd andc and orc tests, failing because RB needs inversion not RA
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 14:11:25 +0000 (15:11 +0100)]
add andc and orc tests, failing because RB needs inversion not RA

4 years agomodsd bug, https://bugs.libre-soc.org/show_bug.cgi?id=471
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 13:01:26 +0000 (14:01 +0100)]
modsd bug, https://bugs.libre-soc.org/show_bug.cgi?id=471

4 years agoFirst draft of a mini-language to describe GTKWave documents
Cesar Strauss [Sat, 22 Aug 2020 12:13:21 +0000 (09:13 -0300)]
First draft of a mini-language to describe GTKWave documents

Uses a split CSS + DOM approach, where style is separated from content.
For the moment, only syntax and semantics definitions are proposed.
Implementation should be the next step.

4 years agosubmodule update
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 12:18:03 +0000 (13:18 +0100)]
submodule update

4 years agoadd regression test for nonzero addis
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 11:24:29 +0000 (12:24 +0100)]
add regression test for nonzero addis

4 years agoadd means to run microwatt test binaries
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 11:23:23 +0000 (12:23 +0100)]
add means to run microwatt test binaries

4 years agor0 zero tests on addis, fails
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 11:09:19 +0000 (12:09 +0100)]
r0 zero tests on addis, fails

4 years agoinvestigating litex sdrinit function
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 10:35:00 +0000 (11:35 +0100)]
investigating litex sdrinit function

4 years agoadd pseudo-op conversion
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 10:32:06 +0000 (11:32 +0100)]
add pseudo-op conversion

4 years agoadd start of litex bios counter loop
Luke Kenneth Casson Leighton [Sat, 22 Aug 2020 10:26:22 +0000 (11:26 +0100)]
add start of litex bios counter loop

4 years agoremove extraneous comments
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 21:07:02 +0000 (22:07 +0100)]
remove extraneous comments

4 years agotesting 64-bit wishbone bus after 32-bit *still* fails ECP5 memtest *sigh*
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 21:05:12 +0000 (22:05 +0100)]
testing 64-bit wishbone bus after 32-bit *still* fails ECP5 memtest *sigh*

4 years agotypo fix in test_l0_cache_buffer2.py
Tobias Platen [Fri, 21 Aug 2020 18:49:14 +0000 (20:49 +0200)]
typo fix in test_l0_cache_buffer2.py

4 years agodcache.py fix asserts, use backslash and two strings, one per line,
Cole Poirier [Fri, 21 Aug 2020 18:12:57 +0000 (11:12 -0700)]
dcache.py fix asserts, use backslash and two strings, one per line,
fixes rest of https://bugs.libre-soc.org/show_bug.cgi?id=469#c2

4 years agodcache.py replace functions that return signals with constants, generate
Cole Poirier [Fri, 21 Aug 2020 18:07:21 +0000 (11:07 -0700)]
dcache.py replace functions that return signals with constants, generate
ranges from constans instead of same functions returned signals, remove
default values from function args, fixes most of https://bugs.libre-soc.org/show_bug.cgi?id=469#c2

4 years agowb_types fix typo
Cole Poirier [Fri, 21 Aug 2020 18:06:52 +0000 (11:06 -0700)]
wb_types fix typo

4 years agoconnect TestCachedMemoryPortInterface to LDSTSplitter
Tobias Platen [Fri, 21 Aug 2020 16:41:54 +0000 (18:41 +0200)]
connect TestCachedMemoryPortInterface to LDSTSplitter

4 years agoget litex sim enabled with 32-bit wishbone bus
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 15:37:10 +0000 (16:37 +0100)]
get litex sim enabled with 32-bit wishbone bus

4 years agold/st bus reduction test operational
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 14:24:06 +0000 (15:24 +0100)]
ld/st bus reduction test operational

4 years agofirst test of down-converted load/store from 64 to 32 bit
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 12:06:03 +0000 (13:06 +0100)]
first test of down-converted load/store from 64 to 32 bit

4 years agofirst test of down-converted load/store from 64 to 32 bit
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 12:05:45 +0000 (13:05 +0100)]
first test of down-converted load/store from 64 to 32 bit

4 years agoadd in WishboneDownConvert into LoadStoreUnitInterface
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 11:41:42 +0000 (12:41 +0100)]
add in WishboneDownConvert into LoadStoreUnitInterface

4 years agocomment formatting
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 11:00:15 +0000 (12:00 +0100)]
comment formatting

4 years agoremove default values
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 10:59:46 +0000 (11:59 +0100)]
remove default values

4 years agojust range(the_constant)
Luke Kenneth Casson Leighton [Fri, 21 Aug 2020 10:57:17 +0000 (11:57 +0100)]
just range(the_constant)

4 years agoMUL pipeline WIP: mullw and mullwu covered.
Samuel A. Falvo II [Fri, 21 Aug 2020 03:20:20 +0000 (20:20 -0700)]
MUL pipeline WIP: mullw and mullwu covered.

4 years agoMUL pipeline: account for overflow flags. WIP
Samuel A. Falvo II [Fri, 21 Aug 2020 02:54:20 +0000 (19:54 -0700)]
MUL pipeline: account for overflow flags.  WIP

4 years agoMerge branch 'master' of git.libre-soc.org:soc
Cole Poirier [Fri, 21 Aug 2020 02:46:37 +0000 (19:46 -0700)]
Merge branch 'master' of git.libre-soc.org:soc

4 years agodcache.py commit today and yesterday's progress (sorry for the delay,
Cole Poirier [Fri, 21 Aug 2020 02:44:41 +0000 (19:44 -0700)]
dcache.py commit today and yesterday's progress (sorry for the delay,
unexpected circumstances led me to not be able to commit yesterday)

4 years agoMUL pipeline proofs: mulli / mullw WIP.
Samuel A. Falvo II [Fri, 21 Aug 2020 01:32:17 +0000 (18:32 -0700)]
MUL pipeline proofs: mulli / mullw WIP.

4 years agoMUL pipeline proof: muldw(u)
Samuel A. Falvo II [Thu, 20 Aug 2020 23:58:11 +0000 (16:58 -0700)]
MUL pipeline proof: muldw(u)

4 years agoMUL pipeline proof: signed mulhw
Samuel A. Falvo II [Thu, 20 Aug 2020 22:30:17 +0000 (15:30 -0700)]
MUL pipeline proof: signed mulhw

4 years agostart wiring TestCachedMemoryPortInterface
Tobias Platen [Thu, 20 Aug 2020 18:47:39 +0000 (20:47 +0200)]
start wiring TestCachedMemoryPortInterface

4 years agotestcase refactoring
Tobias Platen [Thu, 20 Aug 2020 18:11:56 +0000 (20:11 +0200)]
testcase refactoring

4 years agoadd new class TestCachedMemoryPortInterface
Tobias Platen [Thu, 20 Aug 2020 17:34:32 +0000 (19:34 +0200)]
add new class TestCachedMemoryPortInterface

4 years agobugfix wishbone downconvert using wb sram 64-to-32 test
Luke Kenneth Casson Leighton [Thu, 20 Aug 2020 14:28:12 +0000 (15:28 +0100)]
bugfix wishbone downconvert using wb sram 64-to-32 test

4 years agoadd a wishbone upconverter
Luke Kenneth Casson Leighton [Thu, 20 Aug 2020 13:20:15 +0000 (14:20 +0100)]
add a wishbone upconverter

4 years agorename and document fields in shift_rot proof
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 22:03:54 +0000 (23:03 +0100)]
rename and document fields in shift_rot proof

4 years agocomments in dcache
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 18:58:12 +0000 (19:58 +0100)]
comments in dcache

4 years agomore subtle interactions between wishbone bus when there are delays,
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 18:02:30 +0000 (19:02 +0100)]
more subtle interactions between wishbone bus when there are delays,
LD/ST CompUnit and PortInterface

4 years agobit of a reorg of mul proof, tracking down missing
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 06:24:58 +0000 (07:24 +0100)]
bit of a reorg of mul proof, tracking down missing
Assume op.is_32bit == 0 for OP_MUL_H32

4 years agomove long mul tests to separate unit test
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 06:24:00 +0000 (07:24 +0100)]
move long mul tests to separate unit test

4 years agouse "Mask" class which is more gate-efficient than (1<<x)-1
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 04:45:21 +0000 (05:45 +0100)]
use "Mask" class which is more gate-efficient than (1<<x)-1

4 years agoWIP: OP_MUL proofs started.
Samuel A. Falvo II [Wed, 19 Aug 2020 04:12:19 +0000 (21:12 -0700)]
WIP: OP_MUL proofs started.

I am out of my league.  Cannot figure out how to make proof pass.
Committing latest incarnation of proof code.

4 years agoset up StageChain of 3 mul stages
Luke Kenneth Casson Leighton [Wed, 19 Aug 2020 00:15:33 +0000 (01:15 +0100)]
set up StageChain of 3 mul stages

4 years agofu/mul/test/test_pipe_caller.py test case_all_rb_close_to_ov change rb
Cole Poirier [Tue, 18 Aug 2020 21:15:20 +0000 (14:15 -0700)]
fu/mul/test/test_pipe_caller.py test case_all_rb_close_to_ov change rb
dividend from randint(0,1) to randint((-1 << 31), (1 << 31) - 1)