Nicolai Hähnle [Thu, 7 Feb 2019 17:53:27 +0000 (18:53 +0100)]
radeonsi/gfx10: implement si_emit_global_shader_pointers
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Fri, 31 Aug 2018 17:59:48 +0000 (19:59 +0200)]
radeonsi/gfx10: implement si_init_tess_factor_ring
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Fri, 31 Aug 2018 17:59:36 +0000 (19:59 +0200)]
radeonsi/gfx10: initialize EXEC for TES-as-NGG (without geometry shader)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Fri, 31 Aug 2018 17:58:35 +0000 (19:58 +0200)]
radeonsi/gfx10: use correct VGPR for instance ID in LS shader
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Fri, 31 Aug 2018 17:54:59 +0000 (19:54 +0200)]
radeonsi/gfx10: implement si_shader_hs
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Fri, 31 Aug 2018 17:53:52 +0000 (19:53 +0200)]
radeonsi/gfx10: implement si_create_sampler_state
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 30 Aug 2018 15:06:52 +0000 (17:06 +0200)]
radeonsi/gfx10: double the number of tessellation offchip buffers per SE
Each gfx10 shader engine corresponds to two gfx9 shader engines, so scale
the number of offchip buffers accordingly.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 28 Aug 2018 14:00:28 +0000 (16:00 +0200)]
radeonsi/gfx10: implement get_tess_ring_descriptor
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Mon, 23 Jul 2018 07:47:19 +0000 (09:47 +0200)]
radeonsi/gfx10: mask DCC tile swizzle by alignment
DCC alignment can be less than the alignment of the main surface. In that
case, the DCC tile swizzle needs to be masked accordingly. Should have no
impact on pre-gfx10.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Mon, 2 Jul 2018 16:50:48 +0000 (18:50 +0200)]
radeonsi/gfx10: implement hardware MSAA resolve
MSAA is only supported for 64KB_{R,Z}_X modes, so the micro tile
optimization that we use on gfx9 and earlier does not work.
Be very explicit about how the swizzle mode of the temporary surface is
selected.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 21 Jun 2018 12:56:54 +0000 (14:56 +0200)]
radeonsi/gfx10: fix binding on si_update_scratch_relocs
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 19 Jun 2018 15:44:24 +0000 (17:44 +0200)]
radeonsi/gfx10: set llvm_has_working_vgpr_indexing
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Fri, 1 Jun 2018 14:04:02 +0000 (16:04 +0200)]
radeonsi/gfx10: implement load_const_buffer_desc_fast_path
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Fri, 1 Jun 2018 14:03:31 +0000 (16:03 +0200)]
radeonsi/gfx10: take PRIMID from the correct output when exported by GS
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 30 May 2018 20:47:10 +0000 (22:47 +0200)]
radeonsi/gfx10: change location of instance ID shader input
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 30 May 2018 20:45:06 +0000 (22:45 +0200)]
radeonsi/gfx10: set USER_DATA_ADDR offset for geometry shaders
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 7 May 2019 22:54:46 +0000 (00:54 +0200)]
radeonsi/gfx10: implement si_emit_derived_tess_state
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 8 May 2019 01:10:21 +0000 (03:10 +0200)]
radeonsi/gfx10: implement si_shader_gs
This is only used in the legacy, non-NGG path.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 8 May 2019 01:09:42 +0000 (03:09 +0200)]
radeonsi/gfx10: implement preload_ring_buffers
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 14 Nov 2017 15:59:35 +0000 (16:59 +0100)]
radeonsi/gfx10: implement si_set_ring_buffer
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 8 May 2019 00:54:01 +0000 (02:54 +0200)]
radeonsi/gfx10: allow rectangle outputs from NGG primitive shader
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 7 May 2019 23:40:29 +0000 (01:40 +0200)]
radeonsi/gfx10: emit VGT_GS_OUT_PRIM_TYPE from draw and add it to VS_STATE
With NGG, the VGT_GS_OUT_PRIM_TYPE can change without a shader change.
The VS_STATE is required for both streamout and culling from a vertex
shader without pre-compiling outprim-specific variants.
We could consider compiling specialized variants in the future. We
could also consider compiling the NGG logic as an epilog.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 23 May 2018 20:31:41 +0000 (22:31 +0200)]
radeonsi/gfx10: NGG geometry shader PM4 and upload
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 23 May 2018 20:20:15 +0000 (22:20 +0200)]
radeonsi/gfx10: generate geometry shaders for NGG
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 13 Dec 2017 12:25:23 +0000 (13:25 +0100)]
radeonsi/gfx10: use the correct register for image descriptor dumping
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Sun, 19 Nov 2017 14:40:12 +0000 (15:40 +0100)]
radeonsi/gfx10: emit GE_CNTL instead of IA_MULTI_VGT_PARAM for legacy mode
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Sun, 19 Nov 2017 14:24:28 +0000 (15:24 +0100)]
radeonsi/gfx10: initialize GE_{MAX,MIN}_VTX_INDX/INDX_OFFSET
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Sat, 18 Nov 2017 20:16:26 +0000 (21:16 +0100)]
radeonsi/gfx10: setup registers for OpenGL compute
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Sat, 18 Nov 2017 19:55:56 +0000 (20:55 +0100)]
radeonsi/gfx10: set user data base registers
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 7 May 2019 21:50:01 +0000 (23:50 +0200)]
radeonsi/gfx10: implement gfx10_shader_ngg
For pipelines without API GS. We will later expand this to cover NGG
geometry shaders as well.
Note that the vtx offset passed into the GS part is just the
vertex index multiplied by VGT_ESGS_RING_ITEMSIZE.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Sat, 18 Nov 2017 13:32:59 +0000 (14:32 +0100)]
radeonsi/gfx10: add NGG registers to si_init_config
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Sat, 18 Nov 2017 13:32:34 +0000 (14:32 +0100)]
radeonsi/gfx10: update shader-related fields in si_init_config
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Sat, 18 Nov 2017 12:27:55 +0000 (13:27 +0100)]
radeonsi/gfx10: implement si_shader_ps
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 16 Nov 2017 16:00:50 +0000 (17:00 +0100)]
radeonsi/gfx10: generate VS and TES as NGG merged ESGS shaders
This does not support geometry shading yet. Also missing are streamout
and NGG-specific optimizations.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Fri, 17 Nov 2017 12:40:18 +0000 (13:40 +0100)]
radeonsi/gfx10: distinguish between merged shaders and multi-part shaders
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Fri, 17 Nov 2017 12:39:45 +0000 (13:39 +0100)]
radeonsi/gfx10: update si_get_shader_name
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 7 May 2019 21:27:24 +0000 (23:27 +0200)]
radeonsi/gfx10: add as_ngg shader key bit
Also add the shader main part NGG variant, so that in principle
we can switch between legacy in NGG modes.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 16 Nov 2017 16:02:41 +0000 (17:02 +0100)]
radeonsi/gfx10: implement si_update_shaders
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 7 May 2019 21:23:03 +0000 (23:23 +0200)]
radeonsi/gfx10: implement si_build_vgt_shader_config
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 7 May 2019 21:00:43 +0000 (23:00 +0200)]
radeonsi/gfx10: keep track of whether NGG is used
We always use NGG by default, except when tessellation is enabled with
extreme geometry shader amplification.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 16 Nov 2017 16:02:13 +0000 (17:02 +0100)]
radeonsi/gfx10: document NGG shader stages
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 16 Nov 2017 12:33:36 +0000 (13:33 +0100)]
radeonsi/gfx10: implement gfx10_emit_cache_flush
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 16 Nov 2017 11:16:52 +0000 (12:16 +0100)]
radeonsi/gfx10: add si_context::emit_cache_flush
The introduction of GCR_CNTL makes cache flush handling on gfx10
sufficiently different that it makes sense to just use a separate
function.
Since emit_cache_flush is called quite early during context init,
we initialize the pointer explicitly in si_create_context.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 16 Nov 2017 10:18:52 +0000 (11:18 +0100)]
radeonsi/gfx10: implement DB registers
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 16 Nov 2017 09:22:15 +0000 (10:22 +0100)]
radeonsi/gfx10: set CB registers
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 15 Nov 2017 20:29:56 +0000 (21:29 +0100)]
radeonsi/gfx10: always set up sample locations
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 15 Nov 2017 20:10:28 +0000 (21:10 +0100)]
radeonsi/gfx10: use Z32_FLOAT_CLAMP for upgraded depth textures
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 15 Nov 2017 19:50:19 +0000 (20:50 +0100)]
radeonsi/gfx10: implement vertex format changes
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 14 Nov 2017 15:55:34 +0000 (16:55 +0100)]
radeonsi/gfx10: implement si_set_{constant,shader}_buffer
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 7 May 2019 20:43:32 +0000 (22:43 +0200)]
radeonsi/gfx10: implement si_make_buffer_descriptor
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 14 Nov 2017 15:36:16 +0000 (16:36 +0100)]
radeonsi/gfx10: implement si_set_mutable_tex_desc_fields
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 14 Nov 2017 15:10:10 +0000 (16:10 +0100)]
radeonsi/gfx10: gfx10 can render up to 8192 layers
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Sun, 15 Apr 2018 17:09:14 +0000 (19:09 +0200)]
radeonsi/gfx10: add gfx10_make_texture_descriptor
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 14 Nov 2017 15:03:48 +0000 (16:03 +0100)]
radeonsi/gfx10: add pipe_screen::make_texture_descriptor
Texture descriptors in gfx10 are very different.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 14 Nov 2017 14:37:36 +0000 (15:37 +0100)]
radeonsi/gfx10: determine view->is_integer based on the pipe_format
It was convenient, but NUM_FORMAT no longer exists in gfx10.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 14 Nov 2017 14:20:06 +0000 (15:20 +0100)]
radeonsi/gfx10: implement si_is_format_supported
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 14 Nov 2017 14:01:13 +0000 (15:01 +0100)]
radeonsi/gfx10: generate gfx10_format_table.h
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 24 Oct 2017 11:43:30 +0000 (11:43 +0000)]
radeonsi/gfx10: set MAX_ALLOC_COUNT
The number for Vega was copied from PAL and has no effect because of MIN2.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Mon, 13 May 2019 19:58:30 +0000 (21:58 +0200)]
radeonsi/gfx10: require LLVM 9
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Wed, 13 Mar 2019 23:14:13 +0000 (19:14 -0400)]
radeon/vcn: update for new vcn enc interface
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Tue, 5 Mar 2019 22:51:23 +0000 (17:51 -0500)]
radeonsi: enable jpeg decode for navi10
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Tue, 5 Mar 2019 22:49:57 +0000 (17:49 -0500)]
radeon/vcn: implement vcn 2.0 jpeg decode
Use direct register to implement vcn 2.0 jpeg deocde
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Tue, 5 Mar 2019 22:48:52 +0000 (17:48 -0500)]
radeon/vcn: add direct register bool
VCN 2.0 uses direct register space where VCN 1.0 uses some indirect registers
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Tue, 5 Mar 2019 21:51:37 +0000 (16:51 -0500)]
radeon/vcn: add defines for vcn 2.0 jpeg
Add neccesary register defines for vcn 2.0 jpeg deocde
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Sat, 2 Mar 2019 02:14:50 +0000 (21:14 -0500)]
radeon/vcn: use variable to assign ib cmd
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Sat, 2 Mar 2019 02:14:06 +0000 (21:14 -0500)]
radeon/vcn: implement vcn 2.0 encode
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Thu, 1 Nov 2018 19:47:58 +0000 (15:47 -0400)]
radeon/vcn: add vcn2.0 encode skeleton
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
(v2: build fix -- Nicolai)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Thu, 1 Nov 2018 19:35:04 +0000 (15:35 -0400)]
radeon/vcn: move vcn1.0 specific defines to c
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Wed, 31 Oct 2018 18:11:17 +0000 (14:11 -0400)]
radeon/vcn: assign function pointer with ib functions
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Tue, 30 Oct 2018 18:57:59 +0000 (14:57 -0400)]
radeon/vcn: add function pointer for ib functions
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Tue, 30 Oct 2018 18:14:35 +0000 (14:14 -0400)]
radeon/vcn: move header related algorithm to vcn_enc
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Sat, 2 Mar 2019 02:37:20 +0000 (21:37 -0500)]
radeon/vcn: move add buf func to common file
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Boyuan Zhang [Sat, 2 Mar 2019 02:35:59 +0000 (21:35 -0500)]
radeon/vcn: move cs defines to enc header file
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Leo Liu [Mon, 7 Jan 2019 15:29:07 +0000 (10:29 -0500)]
radeon/vcn: add VP9 support for Navi10
It requires bigger DPB and context buffers
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Leo Liu [Tue, 16 Oct 2018 18:18:12 +0000 (14:18 -0400)]
radeonsi: enable encode support for newer HW
Previously it was Raven only allowed to do so
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Leo Liu [Fri, 5 Oct 2018 13:39:15 +0000 (09:39 -0400)]
radeon/vcn: add VCN2 set of internal registers for IB
From VCN2.0, the RBC have different views on the registers
Signed-off-by: Leo Liu <leo.liu@amd.com>
(v2: rebase -- Nicolai)
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Leo Liu [Fri, 5 Oct 2018 13:19:45 +0000 (09:19 -0400)]
radeonsi/uvd: allow newer HW to create HW decoder
Previously it was Raven only allowed to do so
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 28 Jun 2018 19:01:40 +0000 (21:01 +0200)]
ac/surface/gfx10: allow "rotated" micro mode
Standard mode does not support DCC.
The R is retconned to "render target" on gfx10.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 28 Jun 2018 18:53:51 +0000 (20:53 +0200)]
ac/surface/gfx10: DCC is only supported with SW_64KB_{Z,R}_X modes
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 28 Jun 2018 19:03:39 +0000 (21:03 +0200)]
amd/addrlib/gfx10: forbid DCC for swizzle modes which the hardware does not support
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 28 Jun 2018 18:12:05 +0000 (20:12 +0200)]
amd/addrlib/gfx10: fix assertion in Addr2IsValidDisplaySwizzleMode
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Fri, 24 May 2019 12:34:45 +0000 (14:34 +0200)]
amd/common/gfx10: print gfx10 registers in debug dumps
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Sun, 19 Nov 2017 16:26:23 +0000 (17:26 +0100)]
amd/common/gfx10: CMASK is only used for FMASK
All regular color compression is done via DCC.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Mon, 25 Mar 2019 17:12:07 +0000 (18:12 +0100)]
amd/common/gfx10: support new tbuffer encoding
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 29 Nov 2018 23:37:07 +0000 (00:37 +0100)]
amd/common/gfx10: pad shader buffers for instruction prefetch
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 23 May 2018 20:08:22 +0000 (22:08 +0200)]
amd/common/gfx10: implement scan & reduce operations
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 7 May 2019 20:34:50 +0000 (22:34 +0200)]
amd/common/gfx10: add GS_ALLOC_REQ message define
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Sun, 19 Nov 2017 14:23:44 +0000 (15:23 +0100)]
amd/common/gfx10: print out GCR_CNTL as part of {ACQUIRE,RELEASE}_MEM
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 7 May 2019 00:37:19 +0000 (02:37 +0200)]
amd/common/gfx10: add register JSON
A small number of fields now need new disambiguation.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 24 Oct 2017 11:42:31 +0000 (11:42 +0000)]
amd/common: add GFX10 chips
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Marek Olšák [Tue, 2 Jul 2019 18:47:01 +0000 (14:47 -0400)]
meson: require libdrm_amdgpu 2.4.99 for Navi
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Mon, 13 May 2019 19:57:47 +0000 (21:57 +0200)]
radv: gfx10 is not supported
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Marek Olšák [Thu, 20 Jun 2019 00:42:18 +0000 (20:42 -0400)]
amd/addrlib: add gfx10 support
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Fri, 21 Sep 2018 20:07:01 +0000 (22:07 +0200)]
radeonsi: make emit_streamout_output externally accessible
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 20 Sep 2018 08:19:30 +0000 (10:19 +0200)]
radeonsi: pass the context to query destroy functions
We'll need this in the future.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Wed, 24 Apr 2019 13:52:35 +0000 (15:52 +0200)]
radeonsi: make si_restore_qbo_state externally available
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 7 May 2019 20:52:27 +0000 (22:52 +0200)]
radeonsi: make get_primitive_id externally visible
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Thu, 16 Nov 2017 15:49:06 +0000 (16:49 +0100)]
radeonsi: make si_llvm_export_vs externally available
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Nicolai Hähnle [Tue, 7 May 2019 20:38:20 +0000 (22:38 +0200)]
radeonsi: various si_translate_*format functions only apply to pre-gfx10
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Marek Olšák [Thu, 20 Jun 2019 22:32:57 +0000 (18:32 -0400)]
radeonsi: use a fragment shader blit instead of DB->CB copy for ZS CPU mappings
This mainly removes and simplifies code that is no longer needed.
There were some issues with the DB->CB stencil copy on gfx10, so let's
just use a fragment shader blit for all ZS mappings. It's more reliable.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
projects / mesa.git / log