soc.git
4 years agohad to over-ride the wishbone functions on C4M TAP
Luke Kenneth Casson Leighton [Mon, 28 Sep 2020 11:21:31 +0000 (12:21 +0100)]
had to over-ride the wishbone functions on C4M TAP
the default features assume stall, which is not available

4 years agoicache.py fix translation mistake
Cole Poirier [Sun, 27 Sep 2020 16:22:06 +0000 (09:22 -0700)]
icache.py fix translation mistake

4 years agoConvert yet another few tests to be able to use latest cxxsim
Cesar Strauss [Sun, 27 Sep 2020 14:58:06 +0000 (11:58 -0300)]
Convert yet another few tests to be able to use latest cxxsim

4 years agoadd Makefile for creating ls180.il
Luke Kenneth Casson Leighton [Sun, 27 Sep 2020 09:31:13 +0000 (10:31 +0100)]
add Makefile for creating ls180.il

4 years agorename sys_clk_i to clk_24_i
Luke Kenneth Casson Leighton [Sun, 27 Sep 2020 08:17:31 +0000 (09:17 +0100)]
rename sys_clk_i to clk_24_i

4 years agoadd clock selection mechanism
Luke Kenneth Casson Leighton [Sun, 27 Sep 2020 08:08:25 +0000 (09:08 +0100)]
add clock selection mechanism

4 years agoDMI-to-JTAG needed to be "sync" to get ack/resp right
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 23:31:30 +0000 (00:31 +0100)]
DMI-to-JTAG needed to be "sync" to get ack/resp right

4 years agodo not use simdec2 in test_pipe_caller
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 19:57:07 +0000 (20:57 +0100)]
do not use simdec2 in test_pipe_caller

4 years agofix annoying alu test_pipe_caller bug, missing asmcode
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 19:55:10 +0000 (20:55 +0100)]
fix annoying alu test_pipe_caller bug, missing asmcode

4 years agoadd alternative PowerDecode2 to branch test_pipe_caller
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 18:44:42 +0000 (19:44 +0100)]
add alternative PowerDecode2 to branch test_pipe_caller

4 years agoConvert a few more tests to be able to use cxxsim
Cesar Strauss [Sat, 26 Sep 2020 17:30:09 +0000 (14:30 -0300)]
Convert a few more tests to be able to use cxxsim

4 years agotry svf test of DMI MSR
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 17:30:41 +0000 (18:30 +0100)]
try svf test of DMI MSR

4 years agomake check of LDSTMode.update conditional in PowerDecoder2
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 17:30:24 +0000 (18:30 +0100)]
make check of LDSTMode.update conditional in PowerDecoder2

4 years agoadd ls180io.py
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 15:08:45 +0000 (16:08 +0100)]
add ls180io.py

4 years agoadd openocd script to fire off svf test
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 15:08:27 +0000 (16:08 +0100)]
add openocd script to fire off svf test

4 years agoget openocd svf test running, replicating jtag test
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 15:06:42 +0000 (16:06 +0100)]
get openocd svf test running, replicating jtag test

4 years agoput test into "server" mode for connecting with openocd
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 14:51:09 +0000 (15:51 +0100)]
put test into "server" mode for connecting with openocd

4 years agocreate client-server version of jtag debug unit test
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 14:42:24 +0000 (15:42 +0100)]
create client-server version of jtag debug unit test

4 years agocreate client-server version of jtag debug unit test
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 14:41:53 +0000 (15:41 +0100)]
create client-server version of jtag debug unit test

4 years agoclass-ify jtagremote
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 14:13:42 +0000 (15:13 +0100)]
class-ify jtagremote

4 years agosend/receive jtagremote protocol
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 12:28:31 +0000 (13:28 +0100)]
send/receive jtagremote protocol

4 years agobasic client/server socket example
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 11:41:40 +0000 (12:41 +0100)]
basic client/server socket example

4 years agoadd openocd configs
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 11:19:24 +0000 (12:19 +0100)]
add openocd configs

4 years agoreduce sdram pins to smaller address and only 1 cs_n
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 11:17:40 +0000 (12:17 +0100)]
reduce sdram pins to smaller address and only 1 cs_n

4 years agoonly enable pads connections for ls180 for now
Luke Kenneth Casson Leighton [Sat, 26 Sep 2020 11:17:04 +0000 (12:17 +0100)]
only enable pads connections for ls180 for now

4 years agoicache.py fix several subtle bugs that were lines that I had missed from
Cole Poirier [Fri, 25 Sep 2020 20:12:04 +0000 (13:12 -0700)]
icache.py fix several subtle bugs that were lines that I had missed from
icache.vhdl, as well as sneaky incorrect indentations, now it runs,
passing the 'assert valid', but failing on the
'assert insn@0x0000000000000004=00000001', time to use vcd to debug

4 years agowb_types.py add reset value of 0b11111111 for WBSelType, which is the value of the...
Cole Poirier [Fri, 25 Sep 2020 20:08:19 +0000 (13:08 -0700)]
wb_types.py add reset value of 0b11111111 for WBSelType, which is the value of the WBMasterOut object's field 'sel', wich is the 'r.wb.sel' value that appears in both icache.py and dcache.py, source of this reset value is line 614 of icache.vhdl

4 years agoUse nmutil simulator module to simplify choosing among engines
Cesar Strauss [Thu, 24 Sep 2020 22:34:28 +0000 (19:34 -0300)]
Use nmutil simulator module to simplify choosing among engines

4 years agodo not have to use uart_litex gpio_litex names
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 20:17:05 +0000 (21:17 +0100)]
do not have to use uart_litex gpio_litex names

4 years agoadd comments
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 20:00:56 +0000 (21:00 +0100)]
add comments

4 years agoenable GPIO pads through C4M JTAG
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 19:55:10 +0000 (20:55 +0100)]
enable GPIO pads through C4M JTAG

4 years agoc4m iopad integration working
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 19:39:13 +0000 (20:39 +0100)]
c4m iopad integration working

4 years agoicache.py add some missing lines from icache.vhdl, add sram for sim, fix
Cole Poirier [Thu, 24 Sep 2020 19:15:20 +0000 (12:15 -0700)]
icache.py add some missing lines from icache.vhdl, add sram for sim, fix
bug due to main state machine being indednted one level to far an thus
not triggered properly

4 years agomem_types.py wb_types.py add name constructor to all RecordObjects
Cole Poirier [Thu, 24 Sep 2020 17:23:45 +0000 (10:23 -0700)]
mem_types.py wb_types.py add name constructor to all RecordObjects

4 years agoicache.py fixed all errors that raised python exceptions, now runs sim, sim doenst...
Cole Poirier [Thu, 24 Sep 2020 17:20:02 +0000 (10:20 -0700)]
icache.py fixed all errors that raised python exceptions, now runs sim, sim doenst work properly, time to use gtkwave to debug

4 years agoFix whitespace, remove unused imports
Cesar Strauss [Thu, 24 Sep 2020 16:27:53 +0000 (13:27 -0300)]
Fix whitespace, remove unused imports

4 years agobrackets round imports looks cleaner?
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 12:27:33 +0000 (13:27 +0100)]
brackets round imports looks cleaner?

4 years agoadd jtag c4m pins which gives us a way to connect IO pads for JTAG debugging
Luke Kenneth Casson Leighton [Thu, 24 Sep 2020 12:22:00 +0000 (13:22 +0100)]
add jtag c4m pins which gives us a way to connect IO pads for JTAG debugging

4 years agoUse nmutil simulator module to simplify choosing among engines
Cesar Strauss [Thu, 24 Sep 2020 11:45:17 +0000 (08:45 -0300)]
Use nmutil simulator module to simplify choosing among engines

4 years agocs_n and cke in sdram need to match in length
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 21:59:19 +0000 (22:59 +0100)]
cs_n and cke in sdram need to match in length

4 years agochange litex sdram pinouts to ASIC type
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 21:44:56 +0000 (22:44 +0100)]
change litex sdram pinouts to ASIC type

4 years agoredo litex SDCard to send out data/cmd o/i/en pins
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 16:38:58 +0000 (17:38 +0100)]
redo litex SDCard to send out data/cmd o/i/en pins

4 years agosort out GPIO with i/o/oe in ls180
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 15:42:57 +0000 (16:42 +0100)]
sort out GPIO with i/o/oe in ls180

4 years agoadd ls180 pinmap text file
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 14:57:16 +0000 (15:57 +0100)]
add ls180 pinmap text file

4 years agoattempt GPIO bi-directional
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 11:25:37 +0000 (12:25 +0100)]
attempt GPIO bi-directional

4 years agoadd I2C master to ls180
Luke Kenneth Casson Leighton [Wed, 23 Sep 2020 10:43:53 +0000 (11:43 +0100)]
add I2C master to ls180

4 years agoadd 2 PWMs (quick, easy to do)
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 21:47:02 +0000 (22:47 +0100)]
add 2 PWMs (quick, easy to do)

4 years agomove dmi_sim to separate module
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 21:30:02 +0000 (22:30 +0100)]
move dmi_sim to separate module

4 years agoupdate submodule url
Jacob Lifshay [Tue, 22 Sep 2020 18:52:17 +0000 (11:52 -0700)]
update submodule url

4 years agoRevert "disable pia in div tests"
Jacob Lifshay [Tue, 22 Sep 2020 18:42:49 +0000 (11:42 -0700)]
Revert "disable pia in div tests"

Bug #497 resolved as invalid

This reverts commit 05b9baec72be4ef56de2ed56ec12cbf5f7f0eefe.

4 years agoadd openocd.cfg experiment
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 16:12:35 +0000 (17:12 +0100)]
add openocd.cfg experiment

4 years agocreate a JTAG platform and connect it up. jtagremote is actually running
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 14:42:57 +0000 (15:42 +0100)]
create a JTAG platform and connect it up.  jtagremote is actually running

4 years agoadd jtagremote to litex sim, add new "variant" to core.py for jtag
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 14:34:27 +0000 (15:34 +0100)]
add jtagremote to litex sim, add new "variant" to core.py for jtag

4 years agolink litex ls180soc JTAG pads
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 12:19:01 +0000 (13:19 +0100)]
link litex ls180soc JTAG pads

4 years agoadd jtag wishbone and jtag ports to libresoc litex core.py
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 12:10:25 +0000 (13:10 +0100)]
add jtag wishbone and jtag ports to libresoc litex core.py

4 years agoadd jtag interface to issuer_verilog
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 12:01:00 +0000 (13:01 +0100)]
add jtag interface to issuer_verilog

4 years agoadd sys_rst to Clock Reset Generator
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 11:49:49 +0000 (12:49 +0100)]
add sys_rst to Clock Reset Generator

4 years agoadd JTAG IOpads and rename rst to sys_rst
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 11:47:49 +0000 (12:47 +0100)]
add JTAG IOpads and rename rst to sys_rst

4 years agoadd similar platforms to ls180.py
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 11:46:59 +0000 (12:46 +0100)]
add similar platforms to ls180.py

4 years agoadd JTAG bus module
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 11:23:25 +0000 (12:23 +0100)]
add JTAG bus module

4 years agosplit out dmi2jtag into own unit test
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 11:07:35 +0000 (12:07 +0100)]
split out dmi2jtag into own unit test

4 years agosubmodule update
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 10:52:47 +0000 (11:52 +0100)]
submodule update

4 years agoPort soc.experiment.alu_fsm to the new way of invoking cxxsim
Cesar Strauss [Mon, 21 Sep 2020 11:47:13 +0000 (08:47 -0300)]
Port soc.experiment.alu_fsm to the new way of invoking cxxsim

To use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell.
Be sure to check out the cxxsim branch of nMigen, and update yosys to the
latest commit as well.

To use pysim, just keep NMIGEN_SIM_MODE unset. This should be backwards
compatible to old developer versions of nMigen.

Alternatively, when using a recent developer version,
export NMIGEN_SIM_MODE=pysim.

4 years agodisable pia in div tests
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 09:18:51 +0000 (10:18 +0100)]
disable pia in div tests
https://bugs.libre-soc.org/show_bug.cgi?id=497

4 years agoadd MMU (commented out)
Luke Kenneth Casson Leighton [Tue, 22 Sep 2020 08:50:35 +0000 (09:50 +0100)]
add MMU (commented out)

4 years agoadd missing file
Luke Kenneth Casson Leighton [Mon, 21 Sep 2020 18:45:38 +0000 (19:45 +0100)]
add missing file

4 years agoadd quick wishbone jtag test
Luke Kenneth Casson Leighton [Mon, 21 Sep 2020 17:57:47 +0000 (18:57 +0100)]
add quick wishbone jtag test

4 years agoexperiment set dmi msr read
Luke Kenneth Casson Leighton [Mon, 21 Sep 2020 15:44:41 +0000 (16:44 +0100)]
experiment set dmi msr read

4 years agoadd DMI JTAG test
Luke Kenneth Casson Leighton [Mon, 21 Sep 2020 15:37:20 +0000 (16:37 +0100)]
add DMI JTAG test

4 years agoadd JTAG basic unit test
Luke Kenneth Casson Leighton [Mon, 21 Sep 2020 13:47:34 +0000 (14:47 +0100)]
add JTAG basic unit test

4 years agoarg complete rewrite of JTAG2DMI, based it on staf (chips4makers) WB
Luke Kenneth Casson Leighton [Mon, 21 Sep 2020 11:22:26 +0000 (12:22 +0100)]
arg complete rewrite of JTAG2DMI, based it on staf (chips4makers) WB

4 years agoAdd induction proof for the FSM Shifter
Cesar Strauss [Sun, 20 Sep 2020 22:32:46 +0000 (19:32 -0300)]
Add induction proof for the FSM Shifter

4 years agoAdd bounded proof to FSM Shifter
Cesar Strauss [Sun, 20 Sep 2020 22:12:44 +0000 (19:12 -0300)]
Add bounded proof to FSM Shifter

In the process, fix an off-by-one bit size bug.

4 years agoLet the formal engine create some test cases for the FSM Shifter
Cesar Strauss [Sun, 20 Sep 2020 21:03:36 +0000 (18:03 -0300)]
Let the formal engine create some test cases for the FSM Shifter

4 years agoresolve issues in async sim: must not drive async clock from sim.add_clock
Luke Kenneth Casson Leighton [Sun, 20 Sep 2020 18:43:10 +0000 (19:43 +0100)]
resolve issues in async sim: must not drive async clock from sim.add_clock

4 years agostill experimenting with async FF sync
Luke Kenneth Casson Leighton [Sun, 20 Sep 2020 14:39:47 +0000 (15:39 +0100)]
still experimenting with async FF sync

4 years agocontinuing async clock experimenting
Luke Kenneth Casson Leighton [Sun, 20 Sep 2020 14:28:00 +0000 (15:28 +0100)]
continuing async clock experimenting

4 years agoadd an async clock synchronizer experiment
Luke Kenneth Casson Leighton [Sun, 20 Sep 2020 14:20:27 +0000 (15:20 +0100)]
add an async clock synchronizer experiment

4 years agofirst version code-morph on dmi2jtag
Luke Kenneth Casson Leighton [Sun, 20 Sep 2020 11:54:07 +0000 (12:54 +0100)]
first version code-morph on dmi2jtag

4 years agoadd pc_o not connected
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 22:38:13 +0000 (23:38 +0100)]
add pc_o not connected

4 years agoset ROM to empty, set SRAM to tiny 0x200, get things working first
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 22:36:45 +0000 (23:36 +0100)]
set ROM to empty, set SRAM to tiny 0x200, get things working first

4 years agoRemove demonstration code
Cesar Strauss [Sat, 19 Sep 2020 22:14:45 +0000 (19:14 -0300)]
Remove demonstration code

This was moved to nmutil.test.example_gtkwave.

4 years agourk. wishbone slave devices declared incorrectly (I/O inverted) semi_working_ecp5
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 15:00:37 +0000 (16:00 +0100)]
urk. wishbone slave devices declared incorrectly (I/O inverted)

4 years agodisable internal RAM set SRAM to much smaller
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 14:45:07 +0000 (15:45 +0100)]
disable internal RAM set SRAM to much smaller

4 years agoshrink size of SRAM to 8k, move things around
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 14:29:31 +0000 (15:29 +0100)]
shrink size of SRAM to 8k, move things around

4 years agoadd (disabled) tri-state GPIO
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 13:36:25 +0000 (14:36 +0100)]
add (disabled) tri-state GPIO

4 years agoremove the gpio peripheral which was previously hard-linked to interrupts
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 13:10:02 +0000 (14:10 +0100)]
remove the gpio peripheral which was previously hard-linked to interrupts

4 years agoadd 3x EINTs to ls180soc
Luke Kenneth Casson Leighton [Sat, 19 Sep 2020 11:17:34 +0000 (12:17 +0100)]
add 3x EINTs to ls180soc

4 years agoadd SPI, sdcard, preliminary GPIO to ls180 pinouts
Luke Kenneth Casson Leighton [Fri, 18 Sep 2020 22:13:17 +0000 (23:13 +0100)]
add SPI, sdcard, preliminary GPIO to ls180 pinouts

4 years agoargh got fed up trying to shoe-horn into sim.py
Luke Kenneth Casson Leighton [Fri, 18 Sep 2020 21:35:12 +0000 (22:35 +0100)]
argh got fed up trying to shoe-horn into sim.py

4 years agocan remove unneeded overrides of Prev/Next Control
Luke Kenneth Casson Leighton [Fri, 18 Sep 2020 13:11:24 +0000 (14:11 +0100)]
can remove unneeded overrides of Prev/Next Control

4 years agoadd divwe regression test case
Jacob Lifshay [Thu, 17 Sep 2020 22:32:22 +0000 (15:32 -0700)]
add divwe regression test case

4 years agore-enable test case -- no longer goes into an infinite loop
Jacob Lifshay [Thu, 17 Sep 2020 22:31:50 +0000 (15:31 -0700)]
re-enable test case -- no longer goes into an infinite loop

4 years agofix bug #492
Jacob Lifshay [Thu, 17 Sep 2020 22:24:40 +0000 (15:24 -0700)]
fix bug #492

4 years agoreplace sim._state.timeline.now with sim._engine.now
Jacob Lifshay [Thu, 17 Sep 2020 21:30:36 +0000 (14:30 -0700)]
replace sim._state.timeline.now with sim._engine.now

4 years agoadd versa ecp5 fpga litex build script
Luke Kenneth Casson Leighton [Thu, 17 Sep 2020 10:36:43 +0000 (11:36 +0100)]
add versa ecp5 fpga litex build script

4 years agocomplete first translation pass of dmi_dtm_xilinx.vhdl into nmigen,
Cole Poirier [Wed, 16 Sep 2020 22:34:13 +0000 (15:34 -0700)]
complete first translation pass of dmi_dtm_xilinx.vhdl into nmigen,
different sync domains indicated as 'sync = m.d.[SYS|JTAG]_sync', left
some parts undone, didn't rearrange or clean up so Luke can easily
compare with original

4 years agomake a start on LS180 platform
Luke Kenneth Casson Leighton [Wed, 16 Sep 2020 21:54:15 +0000 (22:54 +0100)]
make a start on LS180 platform

4 years agoinitial commit of JTAGToDMI debug interface translated from
Cole Poirier [Wed, 16 Sep 2020 20:48:08 +0000 (13:48 -0700)]
initial commit of JTAGToDMI debug interface translated from
microwatt/dmi_dtm_xilinx.vhdl

4 years agoadd template file/starting point (copy of litex/boards/platforms/ulx3s.py) for asic...
Cole Poirier [Wed, 16 Sep 2020 20:44:38 +0000 (13:44 -0700)]
add template file/starting point (copy of litex/boards/platforms/ulx3s.py) for asic platform that derives from generic platform for 180nm
tapeout