soc.git
4 years agoadd write_cr to ALU record subset
Luke Kenneth Casson Leighton [Sun, 31 May 2020 11:27:45 +0000 (12:27 +0100)]
add write_cr to ALU record subset

4 years agocomment out xer ov/so for now
Luke Kenneth Casson Leighton [Sun, 31 May 2020 10:21:31 +0000 (11:21 +0100)]
comment out xer ov/so for now

4 years agoget carry from cr write_cr
Luke Kenneth Casson Leighton [Sat, 30 May 2020 22:33:40 +0000 (23:33 +0100)]
get carry from cr write_cr

4 years agoselect CR0 write out only when RC=1
Luke Kenneth Casson Leighton [Sat, 30 May 2020 22:31:25 +0000 (23:31 +0100)]
select CR0 write out only when RC=1

4 years agoset CR0 output when OP_CMP or OP_CMPEQB need it
Luke Kenneth Casson Leighton [Sat, 30 May 2020 20:28:13 +0000 (21:28 +0100)]
set CR0 output when OP_CMP or OP_CMPEQB need it

4 years agoadd in use of "Settle"
Luke Kenneth Casson Leighton [Sat, 30 May 2020 19:39:08 +0000 (20:39 +0100)]
add in use of "Settle"

4 years agoadd in write-mask into MultiCompUnit and MCU-ALU unit test: bug detected in
Luke Kenneth Casson Leighton [Sat, 30 May 2020 19:37:10 +0000 (20:37 +0100)]
add in write-mask into MultiCompUnit and MCU-ALU unit test: bug detected in
RC handling

4 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Sat, 30 May 2020 19:12:07 +0000 (21:12 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

4 years agounit test for DataMerger
Tobias Platen [Sat, 30 May 2020 19:11:02 +0000 (21:11 +0200)]
unit test for DataMerger

4 years agocreate read-mask for ALU CompUnit: switches off optional operands
Luke Kenneth Casson Leighton [Sat, 30 May 2020 19:00:33 +0000 (20:00 +0100)]
create read-mask for ALU CompUnit: switches off optional operands

4 years agocreate a write-mask, anything with an "ok" in the Record fields
Luke Kenneth Casson Leighton [Sat, 30 May 2020 18:46:30 +0000 (19:46 +0100)]
create a write-mask, anything with an "ok" in the Record fields

4 years agoallow MultiCompUnit outputs to be Records, to capture Data.ok
Luke Kenneth Casson Leighton [Sat, 30 May 2020 18:39:11 +0000 (19:39 +0100)]
allow MultiCompUnit outputs to be Records, to capture Data.ok

4 years agoadd read-mask to MultiCompUnit
Luke Kenneth Casson Leighton [Sat, 30 May 2020 18:34:08 +0000 (19:34 +0100)]
add read-mask to MultiCompUnit

4 years agocode-shuffle / comments
Luke Kenneth Casson Leighton [Sat, 30 May 2020 18:29:51 +0000 (19:29 +0100)]
code-shuffle / comments

4 years agomess - but a functional mess. ALU-MultiCompUnit semi-functional using pipeline
Luke Kenneth Casson Leighton [Sat, 30 May 2020 15:23:46 +0000 (16:23 +0100)]
mess - but a functional mess.  ALU-MultiCompUnit semi-functional using pipeline

4 years agograb other results from ALU pipeline in compunit test
Luke Kenneth Casson Leighton [Sat, 30 May 2020 13:45:55 +0000 (14:45 +0100)]
grab other results from ALU pipeline in compunit test

4 years agoorder of XER so/ca wrong way round from regspec
Luke Kenneth Casson Leighton [Sat, 30 May 2020 13:27:06 +0000 (14:27 +0100)]
order of XER so/ca wrong way round from regspec

4 years agostill experimenting with ALU-CompUnit interaction
Luke Kenneth Casson Leighton [Sat, 30 May 2020 10:58:30 +0000 (11:58 +0100)]
still experimenting with ALU-CompUnit interaction

4 years agointeresting. use of Settle() works, showing that Regfile is combinatorial on read
Luke Kenneth Casson Leighton [Fri, 29 May 2020 23:51:25 +0000 (00:51 +0100)]
interesting.  use of Settle() works, showing that Regfile is combinatorial on read

4 years agomodule comments for popcount
Luke Kenneth Casson Leighton [Fri, 29 May 2020 21:38:28 +0000 (22:38 +0100)]
module comments for popcount

4 years agocomments on popcount
Luke Kenneth Casson Leighton [Fri, 29 May 2020 21:33:46 +0000 (22:33 +0100)]
comments on popcount

4 years agotrigger ALU ready when operands ready
Luke Kenneth Casson Leighton [Fri, 29 May 2020 16:11:00 +0000 (17:11 +0100)]
trigger ALU ready when operands ready

4 years agofixes for DataMerger
Tobias Platen [Fri, 29 May 2020 16:06:35 +0000 (18:06 +0200)]
fixes for DataMerger

4 years agotrigger read ALU ready/valid from latch as well
Luke Kenneth Casson Leighton [Fri, 29 May 2020 15:49:29 +0000 (16:49 +0100)]
trigger read ALU ready/valid from latch as well

4 years agouse a latch to communicate read/valid output from ALU
Luke Kenneth Casson Leighton [Fri, 29 May 2020 15:30:35 +0000 (16:30 +0100)]
use a latch to communicate read/valid output from ALU

4 years agoDataMerger: rename addr_match_i to addr_array_i
Tobias Platen [Fri, 29 May 2020 15:20:10 +0000 (17:20 +0200)]
DataMerger: rename addr_match_i to addr_array_i

4 years agofixed 'return m is missing'
Tobias Platen [Fri, 29 May 2020 14:43:07 +0000 (16:43 +0200)]
fixed 'return m is missing'

4 years agowhitespace fixes
Tobias Platen [Fri, 29 May 2020 14:40:32 +0000 (16:40 +0200)]
whitespace fixes

4 years agolatch all output on ALU output valid
Luke Kenneth Casson Leighton [Fri, 29 May 2020 13:13:07 +0000 (14:13 +0100)]
latch all output on ALU output valid

4 years agocreate read-done pulse
Luke Kenneth Casson Leighton [Fri, 29 May 2020 12:50:56 +0000 (13:50 +0100)]
create read-done pulse

4 years agowrite-release moves out of "ALU valid" due to using alu_pulse
Luke Kenneth Casson Leighton [Fri, 29 May 2020 12:35:40 +0000 (13:35 +0100)]
write-release moves out of "ALU valid" due to using alu_pulse

4 years agosignal start of request from when ALU triggers result ready
Luke Kenneth Casson Leighton [Fri, 29 May 2020 12:33:45 +0000 (13:33 +0100)]
signal start of request from when ALU triggers result ready

4 years agocreate rising pulse from ALU valid
Luke Kenneth Casson Leighton [Fri, 29 May 2020 12:31:29 +0000 (13:31 +0100)]
create rising pulse from ALU valid

4 years agonames of attributes needs to be dest_o not dest_i
Luke Kenneth Casson Leighton [Fri, 29 May 2020 12:30:06 +0000 (13:30 +0100)]
names of attributes needs to be dest_o not dest_i

4 years agorename output signals in Test ALU
Luke Kenneth Casson Leighton [Fri, 29 May 2020 12:12:06 +0000 (13:12 +0100)]
rename output signals in Test ALU

4 years agoAllow immediate assertion of go in the same cycle as rel
Cesar Strauss [Fri, 29 May 2020 11:09:14 +0000 (08:09 -0300)]
Allow immediate assertion of go in the same cycle as rel

4 years agoCorrect typo
Cesar Strauss [Fri, 29 May 2020 09:30:14 +0000 (06:30 -0300)]
Correct typo

There is no "rd" signal. It's "rel".

4 years agoSend a one-clock "go" pulse after a configurable number of cycles
Cesar Strauss [Thu, 28 May 2020 22:49:04 +0000 (19:49 -0300)]
Send a one-clock "go" pulse after a configurable number of cycles

4 years agomessing about with proof_regfile.py
Luke Kenneth Casson Leighton [Thu, 28 May 2020 23:39:27 +0000 (00:39 +0100)]
messing about with proof_regfile.py

4 years agomove simple_popcount out of class (does not use any class state)
Luke Kenneth Casson Leighton [Thu, 28 May 2020 23:23:05 +0000 (00:23 +0100)]
move simple_popcount out of class (does not use any class state)

4 years agoAdded Initial() synchronous check with draft truth
colepoirier [Thu, 28 May 2020 21:58:03 +0000 (14:58 -0700)]
Added Initial() synchronous check with draft truth
table for rp.ren and wp.wen of Register() in proof_regfile

4 years agoextra check on rd.req in test_alu_compunit
Luke Kenneth Casson Leighton [Thu, 28 May 2020 12:26:21 +0000 (13:26 +0100)]
extra check on rd.req in test_alu_compunit

4 years agoindention
Tobias Platen [Thu, 28 May 2020 18:58:39 +0000 (20:58 +0200)]
indention

4 years agoAdd proof for OP_SETB
Michael Nolan [Thu, 28 May 2020 15:36:41 +0000 (11:36 -0400)]
Add proof for OP_SETB

4 years agoUpdate to latest wiki version
Michael Nolan [Thu, 28 May 2020 15:04:28 +0000 (11:04 -0400)]
Update to latest wiki version

4 years agoAdd OP_SETB
Michael Nolan [Thu, 28 May 2020 15:03:21 +0000 (11:03 -0400)]
Add OP_SETB

4 years agoFix test_isel to properly examine registers
Michael Nolan [Thu, 28 May 2020 14:51:31 +0000 (10:51 -0400)]
Fix test_isel to properly examine registers

4 years agounittest for DataMerger
Tobias Platen [Thu, 28 May 2020 13:05:38 +0000 (15:05 +0200)]
unittest for DataMerger

4 years agomore fixes for DataMerger
Tobias Platen [Thu, 28 May 2020 12:52:02 +0000 (14:52 +0200)]
more fixes for DataMerger

4 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Thu, 28 May 2020 12:23:03 +0000 (14:23 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

4 years agofixes for l0_cache.py
Tobias Platen [Thu, 28 May 2020 12:22:45 +0000 (14:22 +0200)]
fixes for l0_cache.py

4 years agodebug-print rd/wr rel in test_alu_compunit
Luke Kenneth Casson Leighton [Thu, 28 May 2020 12:21:28 +0000 (13:21 +0100)]
debug-print rd/wr rel in test_alu_compunit

4 years agoadd quick test of 3-operand DummyALU in MultiCompALU
Luke Kenneth Casson Leighton [Thu, 28 May 2020 12:10:56 +0000 (13:10 +0100)]
add quick test of 3-operand DummyALU in MultiCompALU

4 years agoadd 3rd parameter to DummyALU
Luke Kenneth Casson Leighton [Thu, 28 May 2020 12:03:38 +0000 (13:03 +0100)]
add 3rd parameter to DummyALU

4 years agodebugging test_alu_compunit.py
Luke Kenneth Casson Leighton [Thu, 28 May 2020 11:55:58 +0000 (12:55 +0100)]
debugging test_alu_compunit.py

4 years agostart on a compunit ALU test
Luke Kenneth Casson Leighton [Thu, 28 May 2020 10:41:24 +0000 (11:41 +0100)]
start on a compunit ALU test

4 years agoupdate comment
Luke Kenneth Casson Leighton [Thu, 28 May 2020 10:33:20 +0000 (11:33 +0100)]
update comment

4 years agoremove trick of not setting SO
Luke Kenneth Casson Leighton [Thu, 28 May 2020 10:27:20 +0000 (11:27 +0100)]
remove trick of not setting SO

4 years agoCheck that rd rises after issue_i, unless it's immediate
Cesar Strauss [Thu, 28 May 2020 10:17:00 +0000 (07:17 -0300)]
Check that rd rises after issue_i, unless it's immediate

4 years agohmm....
Luke Kenneth Casson Leighton [Thu, 28 May 2020 10:10:17 +0000 (11:10 +0100)]
hmm....

4 years agoAdd sync Assert for _wrports 'wen' signal in proof_regfile.py, proof
colepoirier [Thu, 28 May 2020 01:11:25 +0000 (18:11 -0700)]
Add sync Assert for _wrports 'wen' signal in proof_regfile.py, proof
still not working

4 years agoStore and present parameters together with issue_i
Cesar Strauss [Thu, 28 May 2020 00:37:02 +0000 (21:37 -0300)]
Store and present parameters together with issue_i

4 years agodo not use range(0, x) - just range(x)
Luke Kenneth Casson Leighton [Wed, 27 May 2020 19:26:32 +0000 (20:26 +0100)]
do not use range(0, x) - just range(x)

4 years agoremove write-block on register zero
Luke Kenneth Casson Leighton [Wed, 27 May 2020 19:22:13 +0000 (20:22 +0100)]
remove write-block on register zero

4 years agocode-morph, add TODO on OP_RFID, OP_SC, OP_ADDPCIS
Luke Kenneth Casson Leighton [Wed, 27 May 2020 19:19:27 +0000 (20:19 +0100)]
code-morph, add TODO on OP_RFID, OP_SC, OP_ADDPCIS

4 years agoDerive proof_regfile Driver from regfile.Register() so test actually
colepoirier [Wed, 27 May 2020 19:16:06 +0000 (12:16 -0700)]
Derive proof_regfile Driver from regfile.Register() so test actually
runs

4 years agoFix indentation of regfile/formal/proof_regfile.py
colepoirier [Wed, 27 May 2020 18:25:53 +0000 (11:25 -0700)]
Fix indentation of regfile/formal/proof_regfile.py

4 years agoFirst commit of proof of regfile, not working yet
colepoirier [Wed, 27 May 2020 17:25:31 +0000 (10:25 -0700)]
First commit of proof of regfile, not working yet

4 years agoadd LD/ST pipe_data
Luke Kenneth Casson Leighton [Wed, 27 May 2020 17:31:14 +0000 (18:31 +0100)]
add LD/ST pipe_data

4 years agoLogicalOutputData does not need XER.so
Luke Kenneth Casson Leighton [Wed, 27 May 2020 16:12:03 +0000 (17:12 +0100)]
LogicalOutputData does not need XER.so

4 years agocomments
Luke Kenneth Casson Leighton [Wed, 27 May 2020 15:55:10 +0000 (16:55 +0100)]
comments

4 years agoremove XER.ca from logical Input Data - not needed
Luke Kenneth Casson Leighton [Wed, 27 May 2020 15:49:36 +0000 (16:49 +0100)]
remove XER.ca from logical Input Data - not needed

4 years agocleanup logical main proof
Luke Kenneth Casson Leighton [Wed, 27 May 2020 15:40:18 +0000 (16:40 +0100)]
cleanup logical main proof

4 years agocheck cr0, ov and ca ok signals in ALU main_stage proof
Luke Kenneth Casson Leighton [Wed, 27 May 2020 15:27:51 +0000 (16:27 +0100)]
check cr0, ov and ca ok signals in ALU main_stage proof

4 years agoadd carry-out, overflow and cr0 ok setting in ALU main_stage
Luke Kenneth Casson Leighton [Wed, 27 May 2020 15:19:31 +0000 (16:19 +0100)]
add carry-out, overflow and cr0 ok setting in ALU main_stage

4 years agoadd SRR0 to TrapInputData
Luke Kenneth Casson Leighton [Wed, 27 May 2020 14:48:40 +0000 (15:48 +0100)]
add SRR0 to TrapInputData

4 years agoadd links to bugreports into ALu formal proof as well
Luke Kenneth Casson Leighton [Wed, 27 May 2020 14:35:09 +0000 (15:35 +0100)]
add links to bugreports into ALu formal proof as well

4 years agoadd links to bugreports into alu output stage proof
Luke Kenneth Casson Leighton [Wed, 27 May 2020 14:34:01 +0000 (15:34 +0100)]
add links to bugreports into alu output stage proof

4 years agocheck reg output Data.ok in shift_rot formal proof
Luke Kenneth Casson Leighton [Wed, 27 May 2020 14:28:30 +0000 (15:28 +0100)]
check reg output Data.ok in shift_rot formal proof

4 years agorename CROutputData.cr_o to just CROutputData.cr
Luke Kenneth Casson Leighton [Wed, 27 May 2020 14:16:43 +0000 (15:16 +0100)]
rename CROutputData.cr_o to just CROutputData.cr

4 years agotest Data.ok for cr output and full cr output
Luke Kenneth Casson Leighton [Wed, 27 May 2020 14:15:14 +0000 (15:15 +0100)]
test Data.ok for cr output and full cr output

4 years agoassign and test on Data, TODO add Data.ok checking in CR proof
Luke Kenneth Casson Leighton [Wed, 27 May 2020 14:10:00 +0000 (15:10 +0100)]
assign and test on Data, TODO add Data.ok checking in CR proof

4 years agoFix bug in alu main stage proof
Michael Nolan [Wed, 27 May 2020 14:00:57 +0000 (10:00 -0400)]
Fix bug in alu main stage proof

4 years agoMove test case parameters to an "operation" member function
Cesar Strauss [Wed, 27 May 2020 10:06:37 +0000 (07:06 -0300)]
Move test case parameters to an "operation" member function

This allows running several operation cases in succession, without needing
to restart the processes, losing state and trace history.

I expect the need to synchronize the processes for each new operation.

4 years agoMerge branch 'master' of ssh://git.libre-riscv.org:922/soc
Tobias Platen [Wed, 27 May 2020 09:27:19 +0000 (11:27 +0200)]
Merge branch 'master' of ssh://git.libre-riscv.org:922/soc

4 years agoelaborate function for DataMerger
Tobias Platen [Wed, 27 May 2020 09:27:06 +0000 (11:27 +0200)]
elaborate function for DataMerger

4 years agoRemove the monitor process
Cesar Strauss [Wed, 27 May 2020 09:23:58 +0000 (06:23 -0300)]
Remove the monitor process

It may be useful for debugging, but GTKWave is better.
It has served well its purpose, when first setting up the simulation.
Can be added back if needed.

4 years agomake power function unit enum bitmasked
Luke Kenneth Casson Leighton [Wed, 27 May 2020 02:45:40 +0000 (03:45 +0100)]
make power function unit enum bitmasked

4 years agoadd extra INT regs port for now, add Fast Regfile
Luke Kenneth Casson Leighton [Wed, 27 May 2020 00:40:34 +0000 (01:40 +0100)]
add extra INT regs port for now, add Fast Regfile

4 years agoadded XER and CR regfiles, using new VirtualRegPort
Luke Kenneth Casson Leighton [Wed, 27 May 2020 00:34:31 +0000 (01:34 +0100)]
added XER and CR regfiles, using new VirtualRegPort

4 years agocheck assertions
Luke Kenneth Casson Leighton [Tue, 26 May 2020 23:47:53 +0000 (00:47 +0100)]
check assertions

4 years agomake read/write regs properly internal
Luke Kenneth Casson Leighton [Tue, 26 May 2020 23:40:02 +0000 (00:40 +0100)]
make read/write regs properly internal

4 years agoadd VirtualRegPort test, seems to demonstrate it working
Luke Kenneth Casson Leighton [Tue, 26 May 2020 23:14:07 +0000 (00:14 +0100)]
add VirtualRegPort test, seems to demonstrate it working

4 years agoremove sync (not needed)
Luke Kenneth Casson Leighton [Tue, 26 May 2020 22:24:16 +0000 (23:24 +0100)]
remove sync (not needed)

4 years agoget score6600_multi.py working again
Luke Kenneth Casson Leighton [Tue, 26 May 2020 22:17:18 +0000 (23:17 +0100)]
get score6600_multi.py working again

4 years agoredo focus of virtual reg port to do only full datawidth not share with mini-regs
Luke Kenneth Casson Leighton [Tue, 26 May 2020 22:02:47 +0000 (23:02 +0100)]
redo focus of virtual reg port to do only full datawidth not share with mini-regs

4 years agoAdd extras from bottom of the file
Michael Nolan [Tue, 26 May 2020 18:03:30 +0000 (14:03 -0400)]
Add extras from bottom of the file

4 years agoRewrite proof to be more in line with what appears in the wiki
Michael Nolan [Tue, 26 May 2020 17:33:19 +0000 (13:33 -0400)]
Rewrite proof to be more in line with what appears in the wiki

4 years agosort-of (maybe) implemented a virtual port on top of RegFileArray.
Luke Kenneth Casson Leighton [Tue, 26 May 2020 15:54:33 +0000 (16:54 +0100)]
sort-of (maybe) implemented a virtual port on top of RegFileArray.
needs checking

4 years agotry new variant of VirtualRegFile
Luke Kenneth Casson Leighton [Tue, 26 May 2020 15:03:58 +0000 (16:03 +0100)]
try new variant of VirtualRegFile