mesa/st: Tie depth clamp lowering in to the VP code

v1: implemented by Erik Faye-Lund <erik.faye-lund@collabora.com>
v2: Add handling of the ARB_clip_control depth mode
v3: Move depth_range_state to file scope and remove training zeros (Erik)
v4: - don't use the one_shader_variant property, as this is not correct (Marek)
    - also use tests on available shader stages to enable depth_clamp lowering
V5: Don't use key.st, use st directly (Marek)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa/st: add tgsi-lowering code for depth-clamp

This is a TGSI pass that lowers depth-clamping into shader-operations,
by replacing the depth-value with 0 (a z-coordinate of zero will always
pass the OpenGL depth test conditions), and using a dedicated varying to
interpolate the real depth-value instead. Finally we replace the
depth-output in the fragment shader.

v1 implemented by Erik Faye-Lund <erik.faye-lund@collabora.com>
v2: Add support for handling depth clip mode, and refactor code
v3: - Rename *_vs functions to *_last_vertex_stage (Erik)
    - Use 0.0 depth to avoid clipping (Erik)
v4: Fix inversion of bool value for clip control property

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Marek Olšák <marek.olsak@amd.com>

mesa/st: replace boolean declarations by bool

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Reviewed-by: Marek Olšák <marek.olsak@amd.com>

Revert "softpipe: Don't draw when rasterizer_discard is set"

This was too aggressive and breaks TF (Ilia)

This reverts commit 4ee638cd7826e8a4bed76f51c7b73395a2fcdbbc.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

docs: reword meson instructions

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

travis: drop unnecessary Meson option for MacOS

Those are already their default values on MacOS.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>

intel/vec4: Drop all of the 64-bit varying code

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Drop all of the 64-bit varying code

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel: Use NIR to lower 64-bit varying access

Reviewed-by: Matt Turner <mattst88@gmail.com>

nir/lower_io: Add an option to lower 64-bit varyings

Reviewed-by: Matt Turner <mattst88@gmail.com>

docs: Update Platforms and Drivers page with more comprehensive information.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

nir: use common deref has indirect code in scratch lowering.

This doesn't seem to need it's own copy here.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

nir: remove explicit nir_intrinsic_index_flag values

These were left after a rebase and happen to make
NIR_INTRINSIC_SWIZZLE_MASK == NIR_INTRINSIC_SRC_ACCESS, which is how it
was noticed.

Fixes: 6f20643b471a851c936f ("nir: Allow qualifiers on copy_deref and image instructions")
Cc: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

state_tracker: Free Labels for querry and tranform_feedback

Memory leaks were observed on iris with GL_KHR_debug.

Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

iris: Skip emitting 3DSTATE_INDEX_BUFFER if possible

We were emitting 3DSTATE_INDEX_BUFFER on every indexed draw, even if
back-to-back draws referred to the same index buffer.  This improves
drawoverhead scores in the DrawElements cases by about 10%, by giving
us even more minimal batches.

st/dri: simplify dri_get_egl_image by reusing dri2_format_table

this makes dri2_get_mapping_by_fourcc accessible from dri_helpers.h
and does a direct lookup on the fourcc id to match the pipe format

v2 (Ken): Allow map to be NULL, use img->texture->format.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

lima: enable lower_bitops in ppir

The mali pp doesn't support integers and some nir_algebraic
optimizations may result in ops that are not easily lowerable to floats,
so disable optimizations resulting in bitops.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>

nir/algebraic: rename lower_bitshift to lower_bitops

Optimizations that insert bitshift or bitwise operations should not be
applied on GPUs that don't support integer operations.
The .lower_bitshift could be used to control the bitshift related ones,
but there was also one bitwise optimization uncovered.
Since only lima and freedreno use this option and the use case is that
no bit operations are wanted, let's rename it to .lower_bitops and use
it to control all bitops related optimizations.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>

lima/ppir: lower fdot in nir_opt_algebraic

Now that we have fsum in nir, we can move fdot lowering there.
This helps reduce ppir complexity and enables the lowered ops to be part
of other nir optimizations in the optimization loop.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>

nir/algebraic: add new fsum ops and fdot lowering

The Mali400 pp doesn't implement fdot but has fsum3 and fsum4, which can
be used to optimize fdot lowering. fsum2 is not implemented and can be
further lowered to an add with the vector components.
Currently lima ppir handles this lowering internally, however this
happens in a very late stage and requires a big chunk of code compared
to a nir_opt_algebraic lowering.
By having fsum in nir, we can reduce ppir complexity and enable the
lowered ops to be part of other nir optimizations in the optimization
loop.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

lima/ppir: refactor texture code to simplify scheduler

The 'varying fetch' pp instruction deals only with coordinates, and
'texture fetch' deals only with the sampler index.
Previously it was not possible to clearly map ppir_op_load_coords and
ppir_op_load_texture to pp instructions as the source coordinates were
kept in the ppir_op_load_texture node, making this harder to maintain.
The refactor is made with the attempt to clearly map ppir_op_load_coords
to the 'varying fetch' and ppir_op_load_texture to the 'texture fetch'.
The coordinates are still temporarily kept in the ppir_op_load_texture
node as nir has both sampler and coordinates in a single instruction and
it is only possible to output one ppir node during emit. But now after
lowering, the sources are transferred to the (always) created
ppir_op_load_coords node, and it should be possible to directly map them
to their pp instructions from there onwards.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>

lima/ppir: lower texture projection

Lower texture projection in ppir using nir_lower_tex and nir_lower_tex.
This will insert a mul with the coordinate division before the load
varying.

Even though the lima pp supports projection in the load varying
instruction while loading the coordinates (from a register or a
varying), it requires that both the coordinates and projector be
components in a single register.
nir currently handles them in separate ssa, and attempting to merge them
manually may end up in worse code than just doing the coordinate
division manually. So for now let's just lower the projection to add
support for it in lima.
In the future, an optimization pass may be implemented in lima to ensure
that both coords and projector come in the same register, then this
lowering may be disabled and in this case lima may use the built-in
projection and save the mul instruction from lowering.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>

scons: Fix random_r check.

Fixes: 597bddad47e8 ("scons: Test for random_r()")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Matt Turner <mattst88@gmail.com>

Revert "st/dri: simplify dri_get_egl_image by reusing dri2_format_table"

This reverts commit c47af8b95f26bd83efe322ff0baa52263fb8625e.  It causes
dEQP-EGL regressions.  (I think there is an easy fix, but we'll have it
go through review again.)

pan/midgard: Don't special case inline_constant

Another constant source of bugs. Ain't that special.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: De-special-case branching

It's not that special.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Add MALI_SAMP_NORM_COORDS flag

Corresponds to the normalized coordinates? flag on images in OpenCL and
evidently also shows up in GL, so let's wire it in.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Simplify filter_mode definition

It's just a bit field containing some flags; there's no need for all the
macro magic.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: Shrink "compute FBD"

We still don't know what it is, but from a newer trace we now know it's
half the size we thought it was.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Flip texture/sampler fields

We had them backwards in both the command stream and the Midgard stack.
In OpenGL ES 2.0, they're always the same, but in Vulkan/later-GL/CL
they diverge so we can fix this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

panfrost: Add MALI_ATTR_IMAGE value

Images are implemented (in part) as special attributes, so include
support for decoding this.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

st/dri: simplify dri_get_egl_image by reusing dri2_format_table

this makes dri2_get_mapping_by_fourcc accessible from dri_helpers.h
and does a direct lookup on the fourcc id to match the pipe format

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallium: add handling for YUV planar surfaces

st/dri:
this adds a table (similar to the one in i965) which provides
mappings for turning various planar formats into multiple sampler views.
whereas only NV12 and IYUV were supported, now many more formats are
supported here:
* P0XX
* YUV4XX
* YVU4XX
* AYUV
* XYUV
* YUYV
* UYVY

the table is used directly to handle image creation, simplifying
a lot of code and resolving related TODO/FIXME items where workarounds were
previously in place to manage NV12 and IYUV formats exclusively

st/mesa:
the changes here relate to setting up samplers for the planar formats.
this requires:
* checking for driver support for all the sampler formats
* creating the samplers with the corresponding formats and swizzling
* running nir_lower_tex with the appropriate options to trigger the lowering
  for each plane->sampler

fixes kwg/mesa#36

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

gallium: add AYUV and XYUV formats

this only adds the PIPE_FORMAT members, not any direct handling for them

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

pan/midgard: Simplify discard logic

The "branch offset" is, in fact, ignored.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: Add units for more instructions

For everything but freduce, we have some sense of what units the
instruction takes.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: Fix ball/bany opcode table

This were seriously messed up beyond all recognition. How we're passing
shaders.random.* is a mystery.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

pan/midgard: Document branch combination LUT

This took way longer to figure out than it should have..

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>

st/mesa: Skip scissor rect updates when scissor is entirely disabled.

If any scissor rectangles are enabled, then we need to set proper
scissor rectangles for all viewports.  But if the scissor test is
entirely disabled, then we can skip updating any scissor rectangles.

Without this step, we were updating the scissor rectangles based on
the current framebuffer size.  So if an app rendered to a variety of
render targets at different sizes, with scissor test disabled each
time, we'd still be continually updating the scissor rectangles,
even though it's not necessary.

In Civilization VI, this drops us from 310-350 set_scissor_state
calls per frame to 0, as it doesn't appear to use scissor testing.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

egl/drm: ensure the backing gbm is set before using it

Currently, if we error out before gbm_dri is set (say due to a different
name of the backing GBM implementation, or otherwise) the tear down will
trigger a NULL ptr deref and crash out.

Move the gbm_dri initialization as early as possible.

v2: Drop check in dri2_teardowm_drm (Eric)

Reported-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>

docs: update required meson version

Fixes: f7b6a8d12fdc446e3251 ("meson: bump required version to 0.46")
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

radv/gfx10: implement a GE bug workaround

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv/gfx10: remove an obsolete VGT_REUSE_OFF workaround

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv/gfx10: disable LATE_ALLOC_GS on Navi14

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv/gfx10: implement a bug workaround for GE_PC_ALLOC

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv/gfx10: implement a bug workaround for NGG -> legacy transitions

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: skip draw calls with 0-sized index buffers

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

autotools: delete leftover script wrapper

Randomly came across this file, which was likely only used by autotools
to pass arguments to the test.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>

virgl: make use of local variable

Otherwise that variable is only used in an assert() and would need an
ASSERTED to avoid the warning.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: add an ASSERTED

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

compiler/nir: add an ASSERTED

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel: add a couple of ASSERTED

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

tree-wide: replace MAYBE_UNUSED with ASSERTED

Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

r600: replace MAYBE_UNUSED with specific #ifdef

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

gallium/aux: replace MAYBE_UNUSED with UNUSED

MAYBE_UNUSED is going away, so let's replace legitimate uses of it with
UNUSED, which the former aliased to so far anyway.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: replace MAYBE_UNUSED with UNUSED

MAYBE_UNUSED is going away, so let's replace legitimate uses of it with
UNUSED, which the former aliased to so far anyway.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

v3d: replace MAYBE_UNUSED with UNUSED

MAYBE_UNUSED is going away, so let's replace legitimate uses of it with
UNUSED, which the former aliased to so far anyway.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

v3d: drop incorrect MAYBE_UNUSED

While at it, use that `screen` variable everywhere.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

st/tests: drop incorrect MAYBE_UNUSED

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

radv: drop incorrect MAYBE_UNUSED

`compressed` is clearly always used on the line right after.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

r600: move variable to proper scope

It helps show when it's actually used.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

compiler: replace MAYBE_UNUSED with UNUSED

MAYBE_UNUSED is going away, so let's replace legitimate uses of it with
UNUSED, which the former aliased to so far anyway.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

mesa: drop MAYBE_UNUSED var

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

anv: drop MAYBE_UNUSED var

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: drop unused MAYBE_UNUSED function

Added in 1b85c605a60a80975460 but never used.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: replace MAYBE_UNUSED with GEN condition

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel: replace MAYBE_UNUSED with UNUSED

MAYBE_UNUSED is going away, so let's replace legitimate uses of it with
UNUSED, which the former aliased to so far anyway.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel: drop incorrect MAYBE_UNUSED

All these are actually always used.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

egl: replace MAYBE_UNUSED with UNUSED

MAYBE_UNUSED is going away, so let's replace legitimate uses of it with
UNUSED, which the former aliased to so far anyway.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

radv/gfx10: add Wave32 support for compute shaders

It can be enabled with RADV_PERFTEST=cswave32.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

iris: Skip repeated depth buffer disables.

Often times, the depth buffer is entirely disabled, but color render
targets change.  For example, GenerateMipmaps will change the color
render target for each miplevel, but there is no depth buffer.

In the Civilization VI benchmark, this drops the median number of
3DSTATE_DEPTH_BUFFER etc. packets emitted per frame from 472 to 34.

radeonsi: release NIR in the right place to fix crashes

radeonsi: fix packing of key.mono.u.ps

ac/nir: fix incorrect Phis if callbacks use control flow inside control flow

ac/nir: handle abs modifier

ac: fix a memory leak in the error path of ac_build_type_name_for_intr

ac: allow control flow statements in NIR callbacks

This fixes a crash when compiling geometry shaders on radeonsi.

ac/nir: handle negate modifier

radeonsi: don't use lp_build_if for the prim discard compute shader

radeonsi: don't use lp_build_if for the wrapping if block in the VS prolog

radeonsi: don't use lp_build_if for the wrapping if block in merged shaders

radeonsi: don't use lp_build_if (in most common places)

radeonsi: don't use lp_build_alloca

radeonsi/nir: implement FBFETCH for KHR_blend_equation_advanced

radeonsi/nir: set input_interpolate_loc for color inputs

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>

radeonsi/nir: set tgsi_shader_info::num_memory_instructions

radeonsi/nir: accurately set input_usage_mask for doubles (v2)

v2: fix doubles

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi/nir: accurately set output_usagemask (v2)

v2: fix doubles

radeonsi/nir: accurately set reads_*_outputs for TCS

radeonsi/nir: clean up gather_intrinsic_load_deref_input_info

radeonsi/nir: add an option to convert TGSI to NIR

Use at your own risk.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi/nir: clean up some nir_scan_shader code

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi/gfx10: disable DCC image stores

Uncompressed image stores are usually faster.

Also, the driver didn't set WRITE_COMPRESS_ENABLE, so I don't know
what the hw did for image stores.

radeonsi: adjust RB+ blend optimization settings

based on PAL

ac/surface: allow linear swizzle mode automatic selection on gfx9 & 10

let addrlib make the decision to get the same result as PAL.

mesa: add EXT_dsa indexed generic queries

Only GetPointerIndexedvEXT needs an implementation, the other functions are
aliases of existing functions.

mesa: add EXT_dsa indexed texture commands functions

Added functions:
  - EnableClientStateIndexedEXT
  - DisableClientStateIndexedEXT
  - EnableClientStateiEXT
  - DisableClientStateiEXT

Implemented using the idiom provided by the spec:

        if (array == TEXTURE_COORD_ARRAY) {
          int savedClientActiveTexture;

          GetIntegerv(CLIENT_ACTIVE_TEXTURE, &savedClientActiveTexture);
          ClientActiveTexture(TEXTURE0+index);
          XXX(array);
          ClientActiveTexture(savedActiveTexture);
        } else {
          // Invalid enum
        }

mesa: add EXT_dsa (Named)Framebuffer functions

These functions dont support display list as specified:

    Should the selector-free versions of various OpenGL 3.0 and
    EXT_framebuffer_object framebuffer object commands not be allowed
    in display lists [...]?

    RESOLVED:  Yes

mesa: add EXT_dsa NamedBuffer functions

i965/curbe: Look at SYSTEM_VALUE_FRAG_COORD instead of VARYING_SLOT_POS

When transitioning gl_FragCoord over to a system value, we missed one
instance of VARYING_SLOT_POS in i965.  As of this commit, i965 has no
references to VARYING_SLOT_POS.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111263
Fixes: 4bb6e6817ec "intel: Use a system value for gl_FragCoord"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>