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add experiment5
2020-02-25 Luke Kenneth Casson... add experiment5
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2020-02-25 Luke Kenneth Casson... add clk and ck so that ck is recognised for routing
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2020-02-24 Luke Kenneth Casson... add make view
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2020-02-24 Luke Kenneth Casson... bit more experimenting making an ioring around an adder
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2020-02-24 Luke Kenneth Casson... make example as close to adder benchmark as possible
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2020-02-24 Luke Kenneth Casson... simplify experiment4 to an adder, similar to adder...
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2020-02-24 Luke Kenneth Casson... add mksyms.sh
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2020-02-24 Luke Kenneth Casson... whoops yes use clocktree
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2020-02-24 Luke Kenneth Casson... add missing mksym.sh
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2020-02-24 Luke Kenneth Casson... continue experimentation
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2020-02-23 Luke Kenneth Casson... add sm3 to nets
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2020-02-22 Luke Kenneth Casson... correct nets for experiment2
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2020-02-22 Luke Kenneth Casson... track down module in which vdd / vss error exists ...
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2020-02-22 Luke Kenneth Casson... remove working code, shrink "fail" case
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2020-02-22 Luke Kenneth Casson... add test_partsig.py directly to experiment2
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2020-02-22 Luke Kenneth Casson... add ioring experiment
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2020-02-22 Luke Kenneth Casson... add sim just to see if anything happens
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2020-02-22 Luke Kenneth Casson... move Makefile3/4 to experiments3
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2020-02-22 Luke Kenneth Casson... move part_sig_add to its own directory
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2020-02-22 Luke Kenneth Casson... move alu_hier to own directory
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2020-02-22 Luke Kenneth Casson... change coriolis settings, logmode true
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2020-02-21 Luke Kenneth Casson... add extra gitignores
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2020-02-21 Luke Kenneth Casson... add path helpers sys libraries
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2020-02-21 Luke Kenneth Casson... add git ignore file
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2020-02-21 Luke Kenneth Casson... wrong script name
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2020-02-21 Luke Kenneth Casson... remove synthesise-yosys.mk use alliance one
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2020-02-21 Luke Kenneth Casson... add GND/PWR to see what happens in settings.py
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2020-02-21 Luke Kenneth Casson... reduce pmask to stop unconnected bits
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2020-02-21 Luke Kenneth Casson... use alternative experimental class TestAddMod2
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2020-02-20 Luke Kenneth Casson... fix mask width
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2020-02-20 Luke Kenneth Casson... add Makefile3
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2020-02-20 Luke Kenneth Casson... add second Makefile
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2020-02-20 Luke Kenneth Casson... move part_sig_add name
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2020-02-20 Luke Kenneth Casson... run alu_hier.py instead of alu.py (works)
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2020-02-20 Luke Kenneth Casson... remove clock
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2020-02-19 Luke Kenneth Casson... remove clock, use rename on clk in settings
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2020-02-19 Luke Kenneth Casson... increase etesian, set clock to clk
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2020-02-19 Luke Kenneth Casson... use simpler alu rather than alu_hier
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2020-02-19 Luke Kenneth Casson... add clocks and reset and add alu.py as well
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2020-02-19 Luke Kenneth Casson... replace part_sig_add with simpler design
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2020-02-19 Luke Kenneth Casson... add alu_hier.py example
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2020-02-19 Luke Kenneth Casson... replace VLOG with ILANG
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2020-02-19 Luke Kenneth Casson... start running and debugging
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2020-02-19 Luke Kenneth Casson... try symlink to mk fragments
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2020-02-15 Luke Kenneth Casson... remove whitespace
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2020-02-14 Luke Kenneth Casson... add synthesis-yosys.mk with ilang substituted
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2020-02-11 Luke Kenneth Casson... first empty commit
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