| 2020-06-06 |
Luke Kenneth Casson... | Revert "add mksyms.sh"
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| 2020-06-06 |
Luke Kenneth Casson... | add mksyms.sh
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| 2020-06-03 |
Luke Kenneth Casson... | add 16x16 version of FU-FU matrix
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| 2020-05-22 |
Luke Kenneth Casson... | add test_fu_fu_matrix.il
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| 2020-05-22 |
Luke Kenneth Casson... | add test_fu_fu_matrix.il
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| 2020-05-20 |
Luke Kenneth Casson... | add 2nd test matrix
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| 2020-05-20 |
Luke Kenneth Casson... | add dependency matrix example
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| 2020-04-21 |
Luke Kenneth Casson... | automatically located the joining cells between add...
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| 2020-04-21 |
Luke Kenneth Casson... | move get_net_connections to Module in utils.py
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| 2020-04-21 |
Luke Kenneth Casson... | recursive test of get_net_connections
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| 2020-04-21 |
Luke Kenneth Casson... | find connections through plugs
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| 2020-04-21 |
Luke Kenneth Casson... | test out plug/net
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| 2020-04-21 |
Luke Kenneth Casson... | whoops
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| 2020-04-21 |
Luke Kenneth Casson... | move match_instance to Module
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| 2020-04-21 |
Luke Kenneth Casson... | attempt 32-bit width to see if doAlu16Flat.py can cope...
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| 2020-04-21 |
Luke Kenneth Casson... | print debug statement to see what is going on
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| 2020-04-21 |
Luke Kenneth Casson... | whitespace tidyup
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| 2020-04-21 |
Luke Kenneth Casson... | logic/if tidyup
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| 2020-04-21 |
Luke Kenneth Casson... | spelling
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| 2020-04-21 |
Luke Kenneth Casson... | squeeze size a bit more
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| 2020-04-21 |
Luke Kenneth Casson... | corrections getting output routed
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| 2020-04-21 |
Luke Kenneth Casson... | crushed doAlu16Flat down to 465x800
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| 2020-04-21 |
Luke Kenneth Casson... | experimenting crushing alu16 experiment7 down while...
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| 2020-04-06 |
Luke Kenneth Casson... | experimenting with positions
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| 2020-04-06 |
Luke Kenneth Casson... | invert pin-direction to make it sort-of "mirror"
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| 2020-04-06 |
Luke Kenneth Casson... | sort-of got layout positions ok
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| 2020-04-06 |
Luke Kenneth Casson... | weird routing in top right corner, tracks go nowhere
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| 2020-04-06 |
Luke Kenneth Casson... | segfault in katana routing
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| 2020-03-28 |
Luke Kenneth Casson... | set parameters using python style (and auto-detection)
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| 2020-03-26 |
Luke Kenneth Casson... | reduce height of ALU16 slightly (to see if it is possible)
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| 2020-03-21 |
Luke Kenneth Casson... | just a style thing
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| 2020-03-21 |
Luke Kenneth Casson... | remove unused variable
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| 2020-03-21 |
Luke Kenneth Casson... | remove manual add cell library
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| 2020-03-18 |
Luke Kenneth Casson... | whitespace transform
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| 2020-03-17 |
Luke Kenneth Casson... | reposition add and sub, and do place in the *middle...
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| 2020-03-16 |
Luke Kenneth Casson... | add mksym.sh
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| 2020-03-06 |
Luke Kenneth Casson... | add ioring.py (forgot about)
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| 2020-03-04 |
Luke Kenneth Casson... | add cmos to mksym.sh, disable YOSYS_FLATTEN
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| 2020-03-02 |
Luke Kenneth Casson... | add fpmul64.il test, to see how long it takes (10 minutes...
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| 2020-03-01 |
Luke Kenneth Casson... | managed to hack something together to get alu_hier...
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| 2020-02-28 |
Luke Kenneth Casson... | add alu_hier place/route, partially works
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| 2020-02-28 |
Luke Kenneth Casson... | add sub function (class-ish form)
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| 2020-02-28 |
Luke Kenneth Casson... | successful ring created around add.ap
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| 2020-02-28 |
Luke Kenneth Casson... | hmm still not adding traces
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| 2020-02-28 |
Luke Kenneth Casson... | add VIA but metal not working yet
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| 2020-02-28 |
Luke Kenneth Casson... | move add and sub, shrink alu_hier box
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| 2020-02-27 |
Luke Kenneth Casson... | place and route alu_hier, not quite working yet
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| 2020-02-27 |
Luke Kenneth Casson... | do sub layout as well
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| 2020-02-27 |
Luke Kenneth Casson... | "UnManaged Configuration [16843009] = [1+1+0+1,1+0...
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| 2020-02-27 |
Luke Kenneth Casson... | try adding short track manually (doesnt work)
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| 2020-02-27 |
Luke Kenneth Casson... | getting closer to connecting at edge
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| 2020-02-27 |
Luke Kenneth Casson... | successful route but still 40L off the top
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| 2020-02-27 |
Luke Kenneth Casson... | overlap error in routing (two connections on same...
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| 2020-02-26 |
Luke Kenneth Casson... | more experimenting, got cell down to smallest size...
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| 2020-02-26 |
Luke Kenneth Casson... | segfault in pyDoAlu16.py
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| 2020-02-26 |
Luke Kenneth Casson... | experiment with subtractor
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| 2020-02-25 |
Luke Kenneth Casson... | add first experimental hierarchical place/route
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| 2020-02-25 |
Luke Kenneth Casson... | add experiment5
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| 2020-02-25 |
Luke Kenneth Casson... | add clk and ck so that ck is recognised for routing
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| 2020-02-24 |
Luke Kenneth Casson... | add make view
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| 2020-02-24 |
Luke Kenneth Casson... | bit more experimenting making an ioring around an adder
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| 2020-02-24 |
Luke Kenneth Casson... | make example as close to adder benchmark as possible
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| 2020-02-24 |
Luke Kenneth Casson... | simplify experiment4 to an adder, similar to adder...
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| 2020-02-24 |
Luke Kenneth Casson... | add mksyms.sh
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| 2020-02-24 |
Luke Kenneth Casson... | whoops yes use clocktree
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commit | commitdiff | tree |
| 2020-02-24 |
Luke Kenneth Casson... | add missing mksym.sh
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| 2020-02-24 |
Luke Kenneth Casson... | continue experimentation
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| 2020-02-23 |
Luke Kenneth Casson... | add sm3 to nets
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commit | commitdiff | tree |
| 2020-02-22 |
Luke Kenneth Casson... | correct nets for experiment2
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| 2020-02-22 |
Luke Kenneth Casson... | track down module in which vdd / vss error exists ...
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| 2020-02-22 |
Luke Kenneth Casson... | remove working code, shrink "fail" case
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| 2020-02-22 |
Luke Kenneth Casson... | add test_partsig.py directly to experiment2
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| 2020-02-22 |
Luke Kenneth Casson... | add ioring experiment
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| 2020-02-22 |
Luke Kenneth Casson... | add sim just to see if anything happens
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| 2020-02-22 |
Luke Kenneth Casson... | move Makefile3/4 to experiments3
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| 2020-02-22 |
Luke Kenneth Casson... | move part_sig_add to its own directory
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| 2020-02-22 |
Luke Kenneth Casson... | move alu_hier to own directory
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| 2020-02-22 |
Luke Kenneth Casson... | change coriolis settings, logmode true
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| 2020-02-21 |
Luke Kenneth Casson... | add extra gitignores
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commit | commitdiff | tree |
| 2020-02-21 |
Luke Kenneth Casson... | add path helpers sys libraries
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| 2020-02-21 |
Luke Kenneth Casson... | add git ignore file
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commit | commitdiff | tree |
| 2020-02-21 |
Luke Kenneth Casson... | wrong script name
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commit | commitdiff | tree |
| 2020-02-21 |
Luke Kenneth Casson... | remove synthesise-yosys.mk use alliance one
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| 2020-02-21 |
Luke Kenneth Casson... | add GND/PWR to see what happens in settings.py
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| 2020-02-21 |
Luke Kenneth Casson... | reduce pmask to stop unconnected bits
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| 2020-02-21 |
Luke Kenneth Casson... | use alternative experimental class TestAddMod2
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commit | commitdiff | tree |
| 2020-02-20 |
Luke Kenneth Casson... | fix mask width
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commit | commitdiff | tree |
| 2020-02-20 |
Luke Kenneth Casson... | add Makefile3
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commit | commitdiff | tree |
| 2020-02-20 |
Luke Kenneth Casson... | add second Makefile
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commit | commitdiff | tree |
| 2020-02-20 |
Luke Kenneth Casson... | move part_sig_add name
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commit | commitdiff | tree |
| 2020-02-20 |
Luke Kenneth Casson... | run alu_hier.py instead of alu.py (works)
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commit | commitdiff | tree |
| 2020-02-20 |
Luke Kenneth Casson... | remove clock
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commit | commitdiff | tree |
| 2020-02-19 |
Luke Kenneth Casson... | remove clock, use rename on clk in settings
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commit | commitdiff | tree |
| 2020-02-19 |
Luke Kenneth Casson... | increase etesian, set clock to clk
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commit | commitdiff | tree |
| 2020-02-19 |
Luke Kenneth Casson... | use simpler alu rather than alu_hier
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commit | commitdiff | tree |
| 2020-02-19 |
Luke Kenneth Casson... | add clocks and reset and add alu.py as well
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commit | commitdiff | tree |
| 2020-02-19 |
Luke Kenneth Casson... | replace part_sig_add with simpler design
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commit | commitdiff | tree |
| 2020-02-19 |
Luke Kenneth Casson... | add alu_hier.py example
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commit | commitdiff | tree |
| 2020-02-19 |
Luke Kenneth Casson... | replace VLOG with ILANG
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| 2020-02-19 |
Luke Kenneth Casson... | start running and debugging
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