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hook up dcache wb_in/out to PortInterfaceBase Wishbone Record
2021-04-30
Luke Kenneth Casson...
hook up dcache wb_in/out to PortInterfaceBase Wishbone...
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2021-04-30
Luke Kenneth Casson...
sort out spblock 4k sram cell instance name to match...
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2021-04-30
Luke Kenneth Casson...
https://bugs.libre-soc.org/show_bug.cgi?id=635
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2021-04-30
Luke Kenneth Casson...
better reporting on gpr comparisons
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2021-04-30
Luke Kenneth Casson...
set up LoadStore1 in ConfigMemoryPortInterface and...
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2021-04-29
Luke Kenneth Casson...
comment out adding mmu and dcache to pspec in MMU FSM
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2021-04-29
Luke Kenneth Casson...
move dcache into Loadstore1
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2021-04-27
Luke Kenneth Casson...
add option to disable bus forwarding on SPRs and FAST...
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2021-04-27
Luke Kenneth Casson...
add option to enable/disable bus forwarding mode on...
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2021-04-27
Luke Kenneth Casson...
return read data out from Loadstore1 only when valid
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2021-04-26
Luke Kenneth Casson...
hook up MSR into MMU (TODO, use a lot less bits)
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2021-04-26
Luke Kenneth Casson...
simple regression dcache test was faulty. wishbone...
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2021-04-26
Luke Kenneth Casson...
comment read ack in sram
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2021-04-26
Luke Kenneth Casson...
incorrect indentation in dcache rams
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2021-04-26
Luke Kenneth Casson...
simplify dcache test
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2021-04-25
Luke Kenneth Casson...
spelling mistake
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2021-04-25
Luke Kenneth Casson...
remove RegStage1.real_adr temporary from dcache
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2021-04-25
Luke Kenneth Casson...
do not overwrite parameter ra in dcache
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2021-04-25
Luke Kenneth Casson...
comment out dcache_store from test, not the problem
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2021-04-25
Luke Kenneth Casson...
remove unneeded code
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2021-04-25
Luke Kenneth Casson...
read req in wb_in.stall, dcache
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2021-04-25
Luke Kenneth Casson...
add single regression test for dcache
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2021-04-25
Luke Kenneth Casson...
add TODO comment in dcache
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2021-04-25
Luke Kenneth Casson...
move Signals in dcache to relevant context
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2021-04-25
Luke Kenneth Casson...
dcache Elif used where If should have been
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2021-04-25
Luke Kenneth Casson...
whoops should be cyc & ~ack
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2021-04-25
Luke Kenneth Casson...
hard-code dcache stall signal to non-pipelined mode
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2021-04-24
Luke Kenneth Casson...
increase memory size in dcache test
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2021-04-24
Luke Kenneth Casson...
increase size of random dcache testing by 10
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2021-04-24
Luke Kenneth Casson...
fix errors in dcache unit test
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2021-04-24
Luke Kenneth Casson...
whitespace
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2021-04-24
Luke Kenneth Casson...
add additional external libre-soc sphinx references...
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2021-04-24
Luke Kenneth Casson...
add additional external libre-soc sphinx references
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2021-04-24
Luke Kenneth Casson...
remove code moved to openpower-isa repo
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2021-04-23
Luke Kenneth Casson...
add comments on TestIssuer TestRunner
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2021-04-23
Luke Kenneth Casson...
comment tests back in
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2021-04-23
Luke Kenneth Casson...
fix import error
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2021-04-23
Luke Kenneth Casson...
error in setting fast regs test values
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2021-04-23
Luke Kenneth Casson...
import from openpower.tests
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2021-04-23
Luke Kenneth Casson...
whitespace
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2021-04-23
Luke Kenneth Casson...
move logical tests to openpower.test
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2021-04-23
Luke Kenneth Casson...
add trap test cases
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2021-04-23
Luke Kenneth Casson...
move SPR tests to openpower.test
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2021-04-23
Luke Kenneth Casson...
move branch test cases to openpower.test
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2021-04-23
Luke Kenneth Casson...
move LDST tests to openpower.test
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2021-04-23
Luke Kenneth Casson...
move mul tests to openpower.test
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2021-04-23
Luke Kenneth Casson...
move div tests to openpower.test
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2021-04-23
Luke Kenneth Casson...
move div tests to openpower.test
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2021-04-23
Luke Kenneth Casson...
move ALU test cases to openpower.test
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2021-04-23
Luke Kenneth Casson...
move MMU Testcase to openpower.test
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2021-04-23
Luke Kenneth Casson...
move CR test cases to openpower.test
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2021-04-23
Luke Kenneth Casson...
move shiftrot test cases to openpower.test
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2021-04-23
Luke Kenneth Casson...
import from openpower.endian
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2021-04-23
Luke Kenneth Casson...
use openpower.test.common
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2021-04-23
Luke Kenneth Casson...
remove openpower-isa submodule
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2021-04-23
Luke Kenneth Casson...
submodule update, can probably delete it though, now
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2021-04-23
Luke Kenneth Casson...
move more files to openpower-isa
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2021-04-23
Luke Kenneth Casson...
move to import from openpower-isa for reg enums
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2021-04-23
Luke Kenneth Casson...
svanalysis and pywriter now command-line scripts
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2021-04-23
Luke Kenneth Casson...
removed submodule
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2021-04-23
Luke Kenneth Casson...
remove pseudo, moved to openpower-isa
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2021-04-23
Luke Kenneth Casson...
remove simulator directory, moved to openpower-isa
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2021-04-23
Luke Kenneth Casson...
more openpower-isa conversion
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2021-04-23
Luke Kenneth Casson...
correct migration of openpower-isa
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2021-04-23
Luke Kenneth Casson...
more openpower import conversion
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2021-04-23
Luke Kenneth Casson...
more openpower import conversion
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2021-04-23
Luke Kenneth Casson...
move over to from openpower imports
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2021-04-23
Luke Kenneth Casson...
move over to openpower-isa repo
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2021-04-23
Luke Kenneth Casson...
move over to openpower-isa
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2021-04-23
Luke Kenneth Casson...
moving more over to openpower-isa repo
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2021-04-23
Luke Kenneth Casson...
removing more as moved over to openpower-isa
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2021-04-23
Luke Kenneth Casson...
submodule update
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2021-04-22
Luke Kenneth Casson...
add debugging and buffering to CacheRam
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2021-04-22
Luke Kenneth Casson...
whitespace
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2021-04-22
Luke Kenneth Casson...
r1.end_row_ix off-by-one in dcache
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2021-04-22
Luke Kenneth Casson...
sync missing in dcache
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2021-04-22
Luke Kenneth Casson...
dcache.py code-comments
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2021-04-22
Luke Kenneth Casson...
cleanup dcache
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2021-04-22
Luke Kenneth Casson...
error using sync, should have been comb
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2021-04-21
Luke Kenneth Casson...
experimenting with dcache
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2021-04-20
Luke Kenneth Casson...
add enable MMU option to issuer_verilog.py
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2021-04-20
Luke Kenneth Casson...
cannot pass in arguments to Core - must be done with...
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2021-04-20
Luke Kenneth Casson...
use soc.bus.sram instead of nmigen_soc.wishbone.sram
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2021-04-20
Luke Kenneth Casson...
add wishbone sram.py (move from nmigen-soc)
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2021-04-19
Luke Kenneth Casson...
give independent names to spblock512w64b8ws
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2021-04-18
Luke Kenneth Casson...
give spblock512 a name as a submodule
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2021-04-18
Luke Kenneth Casson...
create signal on test_issuer which gives PLL clk_sel_i...
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2021-04-18
Luke Kenneth Casson...
rename SPBlock_512W64B8W to lowercase
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2021-04-18
Luke Kenneth Casson...
submodule update
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2021-04-18
Luke Kenneth Casson...
rename PLL pins to match LIP6.fr PLL
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2021-04-18
Luke Kenneth Casson...
core_stopped_i unused: remove
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2021-04-18
Luke Kenneth Casson...
submodule update
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2021-04-18
Luke Kenneth Casson...
submodule update
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2021-04-18
Luke Kenneth Casson...
add pypi upload to Makefile
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2021-04-18
Luke Kenneth Casson...
add OS Independent classifier
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2021-04-18
Luke Kenneth Casson...
update README
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2021-04-18
Luke Kenneth Casson...
update setup.py to make it "safe" for uploading to...
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2021-04-17
Luke Kenneth Casson...
experiment with alternative PID in radix mmu
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2021-04-17
Luke Kenneth Casson...
pass in SPRs each time on radix test
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2021-04-17
Luke Kenneth Casson...
add LD/ST radix unit test
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