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update docs on compunits
2020-05-23
Luke Kenneth Casson...
update docs on compunits
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2020-05-23
Luke Kenneth Casson...
remove extraneous test_isel
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2020-05-23
Luke Kenneth Casson...
add comments
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2020-05-23
Luke Kenneth Casson...
document purpose of regspec module
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2020-05-23
Luke Kenneth Casson...
split out RegSpecs into separate module
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2020-05-23
Luke Kenneth Casson...
add TODO on multi-in multi-out Function Units
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2020-05-23
Luke Kenneth Casson...
split out RegSpec API into separate class (TODO: move...
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2020-05-23
Luke Kenneth Casson...
add notes on FunctionUnit API
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2020-05-23
Luke Kenneth Casson...
make MultiCompUnit and testing ALU use regspec API...
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2020-05-23
Luke Kenneth Casson...
remove unneeded imports
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2020-05-23
Luke Kenneth Casson...
make demo/test ALU look like nmigen pipeline API
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2020-05-23
Luke Kenneth Casson...
add stub DataMerger class
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2020-05-23
Luke Kenneth Casson...
add link to regspecs on wiki
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2020-05-23
Luke Kenneth Casson...
add regspec capability to MultiCompUnit
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2020-05-23
Luke Kenneth Casson...
make immediate-or-RA selection optional based on awareness...
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2020-05-23
Luke Kenneth Casson...
start to morph MultiCompUnit to take "regspec" as the...
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2020-05-23
Luke Kenneth Casson...
add CR_ISEL formal proof to CR pipeline
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2020-05-23
Luke Kenneth Casson...
add CR_ISEL (and unit test) to CR pipeline
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2020-05-23
Luke Kenneth Casson...
update to (corrected) csv files for CR_ISEL
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2020-05-23
Luke Kenneth Casson...
select bits 2:5 from BC to get CR0 to 7 in DecodeCRin
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2020-05-23
Luke Kenneth Casson...
add gitignore
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2020-05-23
Luke Kenneth Casson...
CR field on Br input data is specd as 0:3 range
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2020-05-23
Luke Kenneth Casson...
add b to CR pipe input data, for isel
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2020-05-22
Luke Kenneth Casson...
add TODO and link to SHIFT_ROT formal bugreport
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2020-05-22
Luke Kenneth Casson...
remove xer.so from ShiftRot formal proof
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2020-05-22
Luke Kenneth Casson...
remove sticky overflow from Shift Rot pipeline
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2020-05-22
Luke Kenneth Casson...
test branch ctr ok flag
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2020-05-22
Luke Kenneth Casson...
cleaner way to test link register ok
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2020-05-22
Luke Kenneth Casson...
whitespace
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2020-05-22
Luke Kenneth Casson...
variable-name munging for branch formal
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2020-05-22
Luke Kenneth Casson...
cleanup logical pipe formal proof
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2020-05-22
Luke Kenneth Casson...
split out Logical Input and Output stages to common...
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2020-05-22
Luke Kenneth Casson...
div probably uses ALU not Logical, needs double-checking...
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2020-05-22
Luke Kenneth Casson...
update comments for ALUCompUnit
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2020-05-22
Luke Kenneth Casson...
soc.fu.logical.input_stage no different from ALU: delete
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2020-05-22
Luke Kenneth Casson...
covert ALU FU to CommonInputStage
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2020-05-22
Luke Kenneth Casson...
create common input pipe spec to avoid code-duplication
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2020-05-22
Luke Kenneth Casson...
move CR over to CompCROpSubset
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2020-05-22
Luke Kenneth Casson...
increase fu-fu test matrix size
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2020-05-22
Luke Kenneth Casson...
remove unneeded code
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2020-05-22
Luke Kenneth Casson...
rename ShiftRot to Mul in fu mul test
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2020-05-22
Luke Kenneth Casson...
rename Logical to Div in fu div test
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2020-05-22
Luke Kenneth Casson...
cookie-cut start on div pipe
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2020-05-22
Luke Kenneth Casson...
add cookie-cut mul pipeline template
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2020-05-22
Luke Kenneth Casson...
whitespace
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2020-05-22
Luke Kenneth Casson...
over 80 chars
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2020-05-22
Luke Kenneth Casson...
comment tidyup
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2020-05-22
Luke Kenneth Casson...
use CompBROpSubset and reduce it down in size (remove...
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2020-05-22
Luke Kenneth Casson...
code-shuffle
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2020-05-22
Luke Kenneth Casson...
remove accidentally added branch input stage
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2020-05-21
Luke Kenneth Casson...
add fu logical_input_record.py
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2020-05-21
Luke Kenneth Casson...
update CROutputData to use Data()
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2020-05-21
Luke Kenneth Casson...
update comments
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2020-05-21
Luke Kenneth Casson...
whitespace cleanup
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2020-05-21
Luke Kenneth Casson...
whitespace cleanup
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2020-05-21
Luke Kenneth Casson...
remove input_cr, output_cr and is_32bit from CompCROpSubset
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2020-05-21
Luke Kenneth Casson...
add read_cr_whole and write_cr_whole to CompCROpSubset
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2020-05-21
Luke Kenneth Casson...
add first cut at cr_input_record.py
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2020-05-21
Luke Kenneth Casson...
move Logical over to use CompLogicalOpSubset
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2020-05-21
Luke Kenneth Casson...
argh syntax error
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2020-05-21
Luke Kenneth Casson...
update and comment CR Input/Output Data specs
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2020-05-21
Luke Kenneth Casson...
add CR out decoder debug
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2020-05-21
Luke Kenneth Casson...
comment CompALUOpSubset, data_len is actually used...
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2020-05-21
Luke Kenneth Casson...
comment DecodeCRIn and DecodeCROut, gratuitously
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2020-05-21
Luke Kenneth Casson...
document subkls in CompUnitRecord
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2020-05-21
Luke Kenneth Casson...
ARSE! frickin git submodules!
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2020-05-21
Luke Kenneth Casson...
move CompLDSTOpSubset to fu.ldst.ldst_input_record
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2020-05-21
Luke Kenneth Casson...
add zero_a flag to CompALUOpSubset
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2020-05-21
Luke Kenneth Casson...
add zero_a flag to Decode2ExecuteType
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2020-05-21
Luke Kenneth Casson...
whitespace/shuffle
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2020-05-21
Luke Kenneth Casson...
move common functionality between PipeSpecs to soc...
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2020-05-21
Luke Kenneth Casson...
move FU IntegerData to directory below
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2020-05-21
Luke Kenneth Casson...
branch output spec nia not cia
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2020-05-21
Luke Kenneth Casson...
add dedicated TrapPipeSpec
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2020-05-21
Luke Kenneth Casson...
create and use ShiftRotPipeSpec
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2020-05-21
Luke Kenneth Casson...
convert to individual PipeSpecs for each pipeline
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2020-05-21
Luke Kenneth Casson...
add regspec to ALUPipeSpec
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2020-05-21
Luke Kenneth Casson...
use branch-specific data structures, add "regspecs...
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2020-05-21
Luke Kenneth Casson...
code-morph LDSTCompUnit to use RecordObject structure...
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2020-05-20
Luke Kenneth Casson...
add link to bugreport in CR pipe formal test
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2020-05-20
Luke Kenneth Casson...
go back to not using LUT in CR pipe
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2020-05-20
Luke Kenneth Casson...
assign index to temporary
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2020-05-20
Luke Kenneth Casson...
store CR lut result in temporary
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2020-05-20
Luke Kenneth Casson...
add register specs to pipeline in/out so that they...
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2020-05-20
Luke Kenneth Casson...
damn. assigning to temporary signals may turn out...
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2020-05-20
Luke Kenneth Casson...
ehn? moo? CR test_pipe_caller locks up 100% CPU on...
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2020-05-20
Luke Kenneth Casson...
correct XER variable names
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2020-05-20
Luke Kenneth Casson...
correct import on shift_rot maskgen
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2020-05-20
Luke Kenneth Casson...
fixup XER names in shift_rot pipe tests
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2020-05-20
Luke Kenneth Casson...
formal proof rename on XER flags
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2020-05-20
Luke Kenneth Casson...
update to new names for XER fields
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2020-05-20
Luke Kenneth Casson...
normalise XER regs carry/32 and SO
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2020-05-20
Luke Kenneth Casson...
add cross-reference to bugtracker and wiki
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2020-05-20
Luke Kenneth Casson...
convert CompUnit to use CompUnitRecord
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2020-05-20
Luke Kenneth Casson...
whitespace, rename ilang to alu_main_stage.il
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2020-05-20
Luke Kenneth Casson...
i seem to like short names that happen to make things...
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2020-05-20
Luke Kenneth Casson...
output ilang for ALU to unique file
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2020-05-20
Luke Kenneth Casson...
use nmutil exts helper in ALU OP_EXTS
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2020-05-20
Luke Kenneth Casson...
use nmutil exts helper
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2020-05-20
Luke Kenneth Casson...
fix imports in fu matrix tests
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