2020-06-08 |
Luke Kenneth Casson... | add traptype and trapaddr to PowerDecoder2. idea is...
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2020-06-08 |
Luke Kenneth Casson... | add traptype and trapaddr to trap_input_data.py
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2020-06-08 |
Luke Kenneth Casson... | add "instr_is_privileged" to power_decoder2 (untested)
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2020-06-08 |
Luke Kenneth Casson... | use 2nd shortened convenience variable in PowerDecoder2
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2020-06-08 |
Luke Kenneth Casson... | use shortened convenience variable in PowerDecoder2
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2020-06-08 |
Luke Kenneth Casson... | re-add unit tests back in
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2020-06-08 |
Luke Kenneth Casson... | add comment docstring about POWER9 simulator
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2020-06-08 |
Luke Kenneth Casson... | more verbose debug information tracking down SO/OV...
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2020-06-08 |
Luke Kenneth Casson... | whoops, overflow-decode (handle_overflow) needed to...
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2020-06-08 |
Luke Kenneth Casson... | add CA/CA32 to write regs fields in parser
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2020-06-08 |
Luke Kenneth Casson... | check that carry has already been done or not by the...
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2020-06-08 |
Luke Kenneth Casson... | code-morph test_core for XER bit clarity
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2020-06-08 |
Luke Kenneth Casson... | set only the SO bit as sticky, not the OV flags as...
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2020-06-08 |
Luke Kenneth Casson... | copy 64-bit OV, try creating 32-bit OV32 in
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2020-06-08 |
Luke Kenneth Casson... | clarify using microwatt calc_ov function.
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2020-06-08 |
Luke Kenneth Casson... | added check which shows that OV32 in "adde." is not...
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2020-06-08 |
Luke Kenneth Casson... | found section in 3.0B PDF that refers to "Program Interrupts"
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2020-06-08 |
Luke Kenneth Casson... | move datamerger proof into standard directory location...
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2020-06-08 |
Luke Kenneth Casson... | copy MSR into SRR1 in trap function
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2020-06-07 |
Luke Kenneth Casson... | update trap with comments
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2020-06-07 |
Luke Kenneth Casson... | update comments
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2020-06-07 |
Luke Kenneth Casson... | assert XER SO/OV/CA registers, check these are ok ...
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2020-06-07 |
Luke Kenneth Casson... | add debug print statements, re-enable all tests in...
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2020-06-07 |
Luke Kenneth Casson... | resolved CR mfcr lookup bug (was in power_decoder. ??)
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2020-06-07 |
Luke Kenneth Casson... | add extra tests for mcrf: shows bug is not directly...
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2020-06-07 |
Luke Kenneth Casson... | how odd. just adding CA32 to self.namespace seems...
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2020-06-07 |
Luke Kenneth Casson... | add extra args to ISA in branch test_pipe_caller
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2020-06-07 |
Luke Kenneth Casson... | add msr to ISA in test_core.py
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2020-06-07 |
Luke Kenneth Casson... | wark-wark, do not & rs[0] into carry-out from rotator
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2020-06-07 |
Luke Kenneth Casson... | ha! set XER CA/CA32 in simulator from output.value...
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2020-06-07 |
Luke Kenneth Casson... | update rotator.py to match microwatt rotator.vhdl
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2020-06-07 |
Luke Kenneth Casson... | add carry test to shift_rot test_pipe_caller: it fails...
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2020-06-07 |
Luke Kenneth Casson... | add extra args to ISA in test_pipe_caller.py
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2020-06-07 |
Luke Kenneth Casson... | add make clean target to qemu_test Makefile
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2020-06-07 |
Luke Kenneth Casson... | optionally writing out CA/CA32 to XER
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2020-06-07 |
Luke Kenneth Casson... | add handling of CA/CA32 in simulator, generated from...
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2020-06-07 |
Luke Kenneth Casson... | add CA/CA32 to list of special regs
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2020-06-07 |
Luke Kenneth Casson... | add missing arg to ISA in test_compunit
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2020-06-07 |
Luke Kenneth Casson... | Revert "if referred to through GPR (GPR[RA]), add to...
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2020-06-07 |
Luke Kenneth Casson... | Revert "remove fixedlogical.patch - added gprs to PowerParse...
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2020-06-07 |
Luke Kenneth Casson... | Revert "add gprs to PowerParser write_regs in p_atom_name"
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2020-06-07 |
Luke Kenneth Casson... | add extra missing args to ISA setup in alu test_pipe_caller
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2020-06-07 |
Luke Kenneth Casson... | if referred to through GPR (GPR[RA]), add to read_regs...
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commit | commitdiff | tree |
2020-06-07 |
Luke Kenneth Casson... | add gprs to PowerParser write_regs in p_atom_name
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commit | commitdiff | tree |
2020-06-07 |
Luke Kenneth Casson... | add missing args to ISA
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commit | commitdiff | tree |
2020-06-07 |
Luke Kenneth Casson... | remove fixedlogical.patch - added gprs to PowerParser...
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2020-06-07 |
Luke Kenneth Casson... | docstring on caller.py inject() decorator
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2020-06-07 |
Luke Kenneth Casson... | add TRAP function, stub
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2020-06-07 |
Luke Kenneth Casson... | update submodule for sprset.mdwn
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commit | commitdiff | tree |
2020-06-07 |
Luke Kenneth Casson... | add MSR to simulator context
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2020-06-07 |
Luke Kenneth Casson... | move MSR_PR checking to separate functiong
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2020-06-06 |
Luke Kenneth Casson... | add python3 env-var if not set in Makefile
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | experimenting with setting up and testing memory
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | expand regwid to 64 in l0_cache test
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | work out how to initialise memory directly
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | initialise L0 Memory from simulator memory
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | wait a little for wr.rel to activate if wrmask is active
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | missing test.mem arg for ISA in test_core
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | allow Mem initialisation in ISACaller
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2020-06-06 |
Luke Kenneth Casson... | shift-mask in Simulator Mem class not quite right
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2020-06-06 |
Luke Kenneth Casson... | write-mask made from LD and Update mode (for data_o...
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | allow Mem in Simulator to be initialised
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2020-06-06 |
Luke Kenneth Casson... | use name of unit to write simulator/vcd file
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2020-06-06 |
Luke Kenneth Casson... | LDSTCompUnit test data structures linked up, starting...
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2020-06-06 |
Luke Kenneth Casson... | allow CompLDSTOpSubset to be passed through to LDSTCompUnit
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | set up LDSTCompUnit using regspec
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | add extra bugreport link
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | whitespace indentation
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | add special-case LDSTFunctionUnit
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | whoops dest%d_o not dest%d_i
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | add beginnings of LDST compunit test
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | whitespace / code-munge
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | comments / whitespace
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | update stage docstring
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | code-munge
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | remove unneeded imports
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commit | commitdiff | tree |
2020-06-06 |
Luke Kenneth Casson... | noticed the regular pattern in all pipe_data.py (regspecs).
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commit | commitdiff | tree |
2020-06-05 |
Luke Kenneth Casson... | comment out CR assertion for now
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commit | commitdiff | tree |
2020-06-05 |
Luke Kenneth Casson... | update comments
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commit | commitdiff | tree |
2020-06-05 |
Luke Kenneth Casson... | add comments and start of elaborate
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commit | commitdiff | tree |
2020-06-05 |
Luke Kenneth Casson... | more comments
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commit | commitdiff | tree |
2020-06-05 |
Luke Kenneth Casson... | more comments
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commit | commitdiff | tree |
2020-06-05 |
Luke Kenneth Casson... | a_i not b_in
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commit | commitdiff | tree |
2020-06-05 |
Luke Kenneth Casson... | add comments
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commit | commitdiff | tree |
2020-06-05 |
Luke Kenneth Casson... | experimenting with CR, not quite right
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commit | commitdiff | tree |
2020-06-05 |
Luke Kenneth Casson... | whoops returning cr2 for cr3 regspec map
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commit | commitdiff | tree |
2020-06-05 |
Luke Kenneth Casson... | name regfile ports by name not numerical position
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commit | commitdiff | tree |
2020-06-05 |
Luke Kenneth Casson... | whoops connecting up CR in wrong order. fixing with...
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commit | commitdiff | tree |
2020-06-05 |
Luke Kenneth Casson... | fix syntax errors and use correct FastRegs (SRR0/1...
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2020-06-05 |
Luke Kenneth Casson... | add TODO for MFSPR/MTSPR
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2020-06-05 |
Luke Kenneth Casson... | refer to srr0/1 not a/b
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2020-06-05 |
Luke Kenneth Casson... | add msr_copy function and use it in OP_TRAP, OP_RFID...
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2020-06-05 |
Luke Kenneth Casson... | set SRR0 in OP_SC
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2020-06-05 |
Luke Kenneth Casson... | add OP_RFID SRR0/SRR1 in PowerDecode2
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2020-06-04 |
Luke Kenneth Casson... | testing CRs after writing: not in the right bit-order
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commit | commitdiff | tree |
2020-06-04 |
Luke Kenneth Casson... | remove unneeded code
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commit | commitdiff | tree |
2020-06-04 |
Luke Kenneth Casson... | use common TestCase class in logical
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2020-06-04 |
Luke Kenneth Casson... | add branch test case to core
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