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set fetch_failed into PowerDecoder2 combinatorially
2021-12-04
Luke Kenneth Casson...
whoops fix up exception happened if alignment triggers...
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2021-12-04
Luke Kenneth Casson...
fix pi_st which should not be trying to wait for the...
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2021-12-04
Luke Kenneth Casson...
fixing DAR updating from exceptions
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2021-12-04
Luke Kenneth Casson...
whoops
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2021-12-04
Luke Kenneth Casson...
MMU lookup DSISR load bit inverted in LoadStore1
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2021-12-04
Luke Kenneth Casson...
store DAR in LoadStore1
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2021-12-04
Luke Kenneth Casson...
not busy if excrption occurs on MMU_LOOKUP in loadstore.py
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2021-12-04
Luke Kenneth Casson...
add means to update dsisr from MMU FSM. TODO: add a...
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2021-12-03
Luke Kenneth Casson...
priv_mode/virt_mode are set in the request, which is...
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2021-12-03
Luke Kenneth Casson...
in loadstore.py set align_intr from request which comes...
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2021-12-03
Luke Kenneth Casson...
driver conflict on priv_mode and virt_mode, do not...
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2021-12-03
Luke Kenneth Casson...
fix up test_loadstore1.py
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2021-12-03
Luke Kenneth Casson...
in loadstore.py, when an exception is done or if the FSM
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2021-12-03
Luke Kenneth Casson...
fix PortInterfaceBase
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2021-12-03
Luke Kenneth Casson...
fix up LDST test functions pi_ld and pi_st to respect...
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2021-12-03
Luke Kenneth Casson...
whitespace
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2021-12-03
Luke Kenneth Casson...
add misaligned ld/st to trigger an exception
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2021-12-03
Luke Kenneth Casson...
comment out dsisr and dar in mmu FSM for now
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2021-12-02
Luke Kenneth Casson...
add a bitvector remap function, the plan is to use...
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2021-12-02
Luke Kenneth Casson...
use new namedtuple in core when calling regspec_decode()
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2021-12-02
Luke Kenneth Casson...
add module parameter to regspec_decode and therefore...
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2021-12-01
Luke Kenneth Casson...
stack of changes to MultiCompUnit to speed it up
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2021-12-01
Luke Kenneth Casson...
experimenting with option to shorten MultiCompUnit...
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2021-12-01
Luke Kenneth Casson...
create single-stage ALU pipeline, shorten latency on...
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2021-12-01
Luke Kenneth Casson...
allow MultiCompUnit to set read and write latches to...
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2021-12-01
Luke Kenneth Casson...
FunctionUnitBaseMulti which derives from ReservationStations2
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2021-12-01
Luke Kenneth Casson...
better name for read latch in core.py
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2021-12-01
Luke Kenneth Casson...
use m.submodules[name] instead of getattr
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2021-12-01
Luke Kenneth Casson...
remove redundant / mis-named variable in core
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2021-12-01
Luke Kenneth Casson...
code-comments
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2021-12-01
Luke Kenneth Casson...
remove unneeded data structure in core
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2021-12-01
Luke Kenneth Casson...
whoops treereduce on write-vector set/clr error
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2021-12-01
Luke Kenneth Casson...
more code-cleanup
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2021-12-01
Luke Kenneth Casson...
use new regspec_decode and fu.get_iospec functions
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2021-12-01
Luke Kenneth Casson...
core tidyup
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2021-12-01
Luke Kenneth Casson...
add Regspecs get_io_spec function
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2021-11-30
Luke Kenneth Casson...
start allocating more FUs (more ReservationStations)
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2021-11-30
Luke Kenneth Casson...
add LogicalTestCases back in to test_core.py (pass)
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2021-11-30
Luke Kenneth Casson...
let PowerDecode2 decide which operand class to use...
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2021-11-30
Luke Kenneth Casson...
use latched readflag (recspec_decode_read "ok") instead...
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2021-11-30
Luke Kenneth Casson...
tidyup on read-flag latches
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2021-11-30
Luke Kenneth Casson...
fix read-decode information by latching not just the...
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2021-11-30
Luke Kenneth Casson...
fix write-after-write hazard checking
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2021-11-30
Luke Kenneth Casson...
allow busy to settle before checking state in test_core.py
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2021-11-30
Luke Kenneth Casson...
only check regs right at the end in test_core.py overlap...
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2021-11-30
Luke Kenneth Casson...
move sim call before core run in test_core.py
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2021-11-30
Luke Kenneth Casson...
getting formerly unused test_core.py operational
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2021-11-29
Luke Kenneth Casson...
whoops missed make_hazard_vec test
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2021-11-29
Luke Kenneth Casson...
whoops do the set/get of the write-vector at a single...
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2021-11-29
Luke Kenneth Casson...
always set fwd_bus_mode=False on regfiles
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2021-11-29
Luke Kenneth Casson...
add MMU and SPR to list of FUs that must report "busy...
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2021-11-29
Luke Kenneth Casson...
disallow overlap in core on LDST, Branch, and Trap.
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2021-11-29
Luke Kenneth Casson...
use dict style not setattr on submodules
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2021-11-27
Luke Kenneth Casson...
code-comments
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2021-11-27
Luke Kenneth Casson...
fix instructions of the type "read-reg-is-same-as-write"
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2021-11-27
Luke Kenneth Casson...
FU-Regs matrix tidyup and comments
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2021-11-27
Luke Kenneth Casson...
minor tidyup on FU-Regs Matrix
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2021-11-27
Luke Kenneth Casson...
update FURegDepMatrix to multi-dest
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2021-11-27
Luke Kenneth Casson...
update naming on Reg_Rsv signals
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2021-11-27
Luke Kenneth Casson...
add copyright and attribution notices
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2021-11-27
Luke Kenneth Casson...
update FU_RW_Pending vectors to multi-dest
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2021-11-27
Luke Kenneth Casson...
convert DependencyRow to multiple destination latches
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2021-11-27
Luke Kenneth Casson...
add copyright and attribution notices to dependence_cell.py
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2021-11-27
Luke Kenneth Casson...
update license and attribution in fu_reg_matrix.py
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2021-11-26
Luke Kenneth Casson...
convert score6600_multi over to using RegSpecs (in...
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2021-11-26
Luke Kenneth Casson...
early use of Array unnecessarily (all uses are static...
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2021-11-26
Luke Kenneth Casson...
early use of Array unnecessarily (all uses are static...
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2021-11-25
Luke Kenneth Casson...
get score6600_multi operational again
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2021-11-25
Luke Kenneth Casson...
add debug prints in old simulator
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2021-11-25
Luke Kenneth Casson...
add debug prints in old simulator
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2021-11-25
Luke Kenneth Casson...
more sorting scoremulti
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2021-11-25
Luke Kenneth Casson...
more sorting out scoremulti
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2021-11-25
Luke Kenneth Casson...
add test pspec for scoremulti to work
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2021-11-24
Luke Kenneth Casson...
convert hazard bitvectors to Reset-Priority SRLatch...
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2021-11-24
Luke Kenneth Casson...
fix write-after-write hazard detection
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2021-11-24
Luke Kenneth Casson...
when allow_overlap enabled do a manual wait until all...
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2021-11-24
Luke Kenneth Casson...
code-comments
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2021-11-24
Luke Kenneth Casson...
add write-after-write hazard detection
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2021-11-24
Luke Kenneth Casson...
add 2nd hazard bitvector port for write-after-write
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2021-11-24
Luke Kenneth Casson...
whoops merged the two write-ports for RT and RA-with...
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2021-11-24
Luke Kenneth Casson...
disable hazard vectors when overlap is not requested...
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2021-11-23
Luke Kenneth Casson...
update submodules
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2021-11-23
Luke Kenneth Casson...
more comments
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2021-11-23
Luke Kenneth Casson...
add FU write-after-write hazard detection Signal (dummy...
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2021-11-23
Luke Kenneth Casson...
add code-comments, link to in-order core
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2021-11-23
Luke Kenneth Casson...
more use of namedtuples in core.py for clarity
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2021-11-23
Luke Kenneth Casson...
start some use of namedtuples in core.py
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2021-11-23
Luke Kenneth Casson...
use some namedtuples to make things clearer in core.py
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2021-11-23
Luke Kenneth Casson...
use fascinating trick of defaultdict-of-defaultdicts
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2021-11-22
Luke Kenneth Casson...
make FetchFSM take PC as an input in its ispec
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2021-11-22
Luke Kenneth Casson...
local variable rename in FetchFSM
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2021-11-22
Luke Kenneth Casson...
split out FetchFSM into separate module
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2021-11-22
Luke Kenneth Casson...
whoops accidentally committed commented-out test for...
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2021-11-21
Luke Kenneth Casson...
reset execute back to ISSUE_START if at INSN_WAIT and
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2021-11-21
Luke Kenneth Casson...
restrict (refine) hazard selection to the one being...
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2021-11-21
Luke Kenneth Casson...
block picker hazard on input to PriorityPicker rather...
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2021-11-21
Luke Kenneth Casson...
parse test_issuer args allow option "allow-overlap...
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2021-11-21
Luke Kenneth Casson...
complex. TestRunner now does not work properly unless...
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2021-11-21
Luke Kenneth Casson...
fixed issue with hazard dependencies, read will nott
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2021-11-19
Luke Kenneth Casson...
add both bitdict and selected args to connect_rd/wrport
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