2020-08-23 |
Luke Kenneth Casson... | comment why litex sim mem map is altered
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2020-08-23 |
Luke Kenneth Casson... | multiply does not have invert_in, zero_a or invert_out
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2020-08-22 |
Luke Kenneth Casson... | rename invert_a to invert_in because logical inverts RB
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2020-08-22 |
Luke Kenneth Casson... | update submodule
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2020-08-22 |
Luke Kenneth Casson... | load bios not 1.bin unit test
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2020-08-22 |
Luke Kenneth Casson... | add extra div regression tests
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2020-08-22 |
Luke Kenneth Casson... | add eqv to logical unit test
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2020-08-22 |
Luke Kenneth Casson... | add nor and nand to unit test
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2020-08-22 |
Luke Kenneth Casson... | moved to div pipe temporarily in compunits
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2020-08-22 |
Luke Kenneth Casson... | bug in andc and orc, complement was taking place on...
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2020-08-22 |
Luke Kenneth Casson... | extend addis test
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2020-08-22 |
Luke Kenneth Casson... | add andc and orc tests, failing because RB needs inversion...
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2020-08-22 |
Luke Kenneth Casson... | modsd bug, https://bugs.libre-soc.org/show_bug.cgi...
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2020-08-22 |
Luke Kenneth Casson... | submodule update
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2020-08-22 |
Luke Kenneth Casson... | add regression test for nonzero addis
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2020-08-22 |
Luke Kenneth Casson... | add means to run microwatt test binaries
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2020-08-22 |
Luke Kenneth Casson... | r0 zero tests on addis, fails
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2020-08-22 |
Luke Kenneth Casson... | investigating litex sdrinit function
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2020-08-22 |
Luke Kenneth Casson... | add pseudo-op conversion
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2020-08-22 |
Luke Kenneth Casson... | add start of litex bios counter loop
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2020-08-21 |
Luke Kenneth Casson... | remove extraneous comments
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2020-08-21 |
Luke Kenneth Casson... | testing 64-bit wishbone bus after 32-bit *still* fails...
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2020-08-21 |
Luke Kenneth Casson... | get litex sim enabled with 32-bit wishbone bus
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2020-08-21 |
Luke Kenneth Casson... | ld/st bus reduction test operational
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2020-08-21 |
Luke Kenneth Casson... | first test of down-converted load/store from 64 to...
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2020-08-21 |
Luke Kenneth Casson... | first test of down-converted load/store from 64 to...
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2020-08-21 |
Luke Kenneth Casson... | add in WishboneDownConvert into LoadStoreUnitInterface
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2020-08-21 |
Luke Kenneth Casson... | comment formatting
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2020-08-21 |
Luke Kenneth Casson... | remove default values
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2020-08-21 |
Luke Kenneth Casson... | just range(the_constant)
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2020-08-20 |
Luke Kenneth Casson... | bugfix wishbone downconvert using wb sram 64-to-32...
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2020-08-20 |
Luke Kenneth Casson... | add a wishbone upconverter
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2020-08-19 |
Luke Kenneth Casson... | rename and document fields in shift_rot proof
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2020-08-19 |
Luke Kenneth Casson... | comments in dcache
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2020-08-19 |
Luke Kenneth Casson... | more subtle interactions between wishbone bus when...
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2020-08-19 |
Luke Kenneth Casson... | bit of a reorg of mul proof, tracking down missing
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2020-08-19 |
Luke Kenneth Casson... | move long mul tests to separate unit test
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2020-08-19 |
Luke Kenneth Casson... | use "Mask" class which is more gate-efficient than...
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2020-08-19 |
Luke Kenneth Casson... | set up StageChain of 3 mul stages
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2020-08-18 |
Luke Kenneth Casson... | fix spr state test
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2020-08-18 |
Luke Kenneth Casson... | add comment in dcache.py
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2020-08-17 |
Luke Kenneth Casson... | move Mask to nmutil
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2020-08-17 |
Luke Kenneth Casson... | turn SelectableInt less/greater into signed versions.
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2020-08-17 |
Luke Kenneth Casson... | use longer memtest in litex sim
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2020-08-17 |
Luke Kenneth Casson... | adjust litex bios cmp test
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2020-08-17 |
Luke Kenneth Casson... | fix signed variants of cmp in alu
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2020-08-17 |
Luke Kenneth Casson... | add new cmp test for alu
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2020-08-17 |
Luke Kenneth Casson... | use shift module in mmu. to be moved to nmutil
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2020-08-16 |
Luke Kenneth Casson... | attempting to track down bug in litex bios memtest
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2020-08-16 |
Luke Kenneth Casson... | read delay on getting regfile data
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2020-08-16 |
Luke Kenneth Casson... | limit debug reporting in litex sim to range of pc
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2020-08-16 |
Luke Kenneth Casson... | cmp test from litex bios
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2020-08-16 |
Luke Kenneth Casson... | remove vhdl comments
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2020-08-16 |
Luke Kenneth Casson... | use simple one-line mask-generation
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2020-08-16 |
Luke Kenneth Casson... | fix LD/ST pimem issue with rising_edge detection
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2020-08-16 |
Luke Kenneth Casson... | missing vars, spelling corrections
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2020-08-16 |
Luke Kenneth Casson... | big reorg, shuffle code to functions, makes the FSM...
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2020-08-16 |
Luke Kenneth Casson... | spelling error, move perm_ok to local
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2020-08-16 |
Luke Kenneth Casson... | more comment removal
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2020-08-16 |
Luke Kenneth Casson... | more remove comments
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2020-08-16 |
Luke Kenneth Casson... | removing more comments, tidyup
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2020-08-16 |
Luke Kenneth Casson... | restore incorrect removal of zero-Cat at LHS (should...
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2020-08-16 |
Luke Kenneth Casson... | continue tidyup, comment removal/review. use byte_reverse...
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2020-08-16 |
Luke Kenneth Casson... | fix batch of syntax errors found by running mmu.py
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2020-08-16 |
Luke Kenneth Casson... | begin tidyup, removing comments after line-by-line...
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2020-08-15 |
Luke Kenneth Casson... | thanks to daveshah, added simulation of dram
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2020-08-15 |
Luke Kenneth Casson... | rather big change to interaction between regfile and...
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2020-08-15 |
Luke Kenneth Casson... | clear compalu data latch always on issue
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2020-08-14 |
Luke Kenneth Casson... | remove latchregister, use sync to capture compunit...
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2020-08-14 |
Luke Kenneth Casson... | ha! "state" (pc, msr) not properly passed to core
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2020-08-14 |
Luke Kenneth Casson... | drop in insn_state synchronously in issuer, at same...
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2020-08-14 |
Luke Kenneth Casson... | submodule update
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2020-08-14 |
Luke Kenneth Casson... | hrfid unit test sets up HSRR0 and HSRR1
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2020-08-14 |
Luke Kenneth Casson... | bad hack to get HSRR0/1 to be "same" as SRR0/1
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2020-08-14 |
Luke Kenneth Casson... | bug in isa parser not recognising MSR as declared variable
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2020-08-14 |
Luke Kenneth Casson... | hack to get hrfid not to alter msr 51
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2020-08-14 |
Luke Kenneth Casson... | stop trying to read swap files
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2020-08-14 |
Luke Kenneth Casson... | sync on alu results in compalu
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2020-08-14 |
Luke Kenneth Casson... | update submodule, add hrfid
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commit | commitdiff | tree |
2020-08-14 |
Luke Kenneth Casson... | update submodule, add hrfid
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2020-08-14 |
Luke Kenneth Casson... | finally, fix decoder combinatorial loop
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2020-08-14 |
Luke Kenneth Casson... | fix test_compunit.py after moving decoder rdflags function
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2020-08-14 |
Luke Kenneth Casson... | add hrfid unit test
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2020-08-14 |
Luke Kenneth Casson... | sync up the core decode-execute state,
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2020-08-14 |
Luke Kenneth Casson... | move instruction decoder out of core
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2020-08-14 |
Luke Kenneth Casson... | move regspec / rdflag decoding functions out of PowerDecode2
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2020-08-14 |
Luke Kenneth Casson... | sort out instruction stop/cancel when adding a new...
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2020-08-14 |
Luke Kenneth Casson... | put multi-ports back (for read) on int and fast regfiles
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2020-08-14 |
Luke Kenneth Casson... | reduce decoder pathways when exception occurs
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2020-08-14 |
Luke Kenneth Casson... | divide shiftrot pipeline into 2 (simple last)
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2020-08-14 |
Luke Kenneth Casson... | divide alu pipeline into 2 (simple last)
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commit | commitdiff | tree |
2020-08-14 |
Luke Kenneth Casson... | divide logical pipe into 2 (simple phase last)
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2020-08-13 |
Luke Kenneth Casson... | fix dmi reg read
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2020-08-13 |
Luke Kenneth Casson... | code-shuffle
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2020-08-13 |
Luke Kenneth Casson... | remove use of latchregigister, replace with sync on...
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2020-08-13 |
Luke Kenneth Casson... | sync on pc writing when changed
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2020-08-13 |
Luke Kenneth Casson... | sync on reset in compalu
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2020-08-13 |
Luke Kenneth Casson... | add forwarding-bus mode to Regfile Memory (and disable it)
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2020-08-13 |
Luke Kenneth Casson... | sync on port interface address in ld/st compunit, and...
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2020-08-13 |
Luke Kenneth Casson... | another sync to cut latency
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