2020-06-04 |
Luke Kenneth Casson... | docstring for AllFunctionUnits
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2020-06-04 |
Luke Kenneth Casson... | missing a fastregs write-port
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2020-06-04 |
Luke Kenneth Casson... | update docstring on simple/core.py
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2020-06-04 |
Luke Kenneth Casson... | move regfile/spec organiser to separate function
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2020-06-04 |
Luke Kenneth Casson... | mention convenience variables
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2020-06-04 |
Luke Kenneth Casson... | rename trap to use convenience variables
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2020-06-04 |
Luke Kenneth Casson... | collate fu-enable signals
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2020-06-04 |
Luke Kenneth Casson... | connect up Function Unit operand subsets
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2020-06-03 |
Luke Kenneth Casson... | forgot to add in rdflag enable
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2020-06-03 |
Luke Kenneth Casson... | whoops, regfiles are uppercase
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2020-06-03 |
Luke Kenneth Casson... | whoops needed a bit of a reorg of the data structure...
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2020-06-03 |
Luke Kenneth Casson... | hmmm got naming wrong in regfile-fu connectivity
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2020-06-03 |
Luke Kenneth Casson... | whoops names of regfiles are lower-case
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2020-06-03 |
Luke Kenneth Casson... | munge/redirect the regfile port based on the naming
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2020-06-03 |
Luke Kenneth Casson... | connect read-enable and src_i to regfile ports
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2020-06-03 |
Luke Kenneth Casson... | link up PriorityPickers on read channels
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2020-06-03 |
Luke Kenneth Casson... | put rdspecs into a different dictionary
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2020-06-03 |
Luke Kenneth Casson... | start putting a non-production core together,
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2020-06-03 |
Luke Kenneth Casson... | add a simple core, not intended for production use
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2020-06-03 |
Luke Kenneth Casson... | correct comments on regspec decode map
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2020-06-03 |
Luke Kenneth Casson... | only select xer_xo if OE enabled
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2020-06-03 |
Luke Kenneth Casson... | decide to elaborate Refiles *into* another class, rather...
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2020-06-03 |
Luke Kenneth Casson... | turn RegFiles into module, add all regfiles to it
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2020-06-03 |
Luke Kenneth Casson... | add a simple class containing all FunctionUnits
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2020-06-03 |
Luke Kenneth Casson... | add class containing all regfiles
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2020-06-03 |
Luke Kenneth Casson... | whitespace
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2020-06-03 |
Luke Kenneth Casson... | use common get_cu_inputs for CR unit tests
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2020-06-03 |
Luke Kenneth Casson... | convert shift_rot tests to use common get_cu_inputs...
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2020-06-03 |
Luke Kenneth Casson... | reorganise ALU tests, move get_cu_inputs function to...
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2020-06-03 |
Luke Kenneth Casson... | worked out how to dynamically enable carry-in to ALU...
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2020-06-03 |
Luke Kenneth Casson... | correct overflow-enable flags for rdmask specs in ALU
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2020-06-03 |
Luke Kenneth Casson... | attempt to make carry-in and overflow-enable optional...
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2020-06-03 |
Luke Kenneth Casson... | remove rdflags in pipe_data.py (redundant)
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2020-06-03 |
Luke Kenneth Casson... | move over to using power_regspec_map.py from PowerDecode2...
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2020-06-03 |
Luke Kenneth Casson... | move obtaining simulator data into common function...
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2020-06-03 |
Luke Kenneth Casson... | mention TODO on SPR regfile
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2020-06-03 |
Luke Kenneth Casson... | tidyup branch. comments
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2020-06-03 |
Luke Kenneth Casson... | convenience variables
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2020-06-03 |
Luke Kenneth Casson... | FormX not FormXL
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2020-06-03 |
Luke Kenneth Casson... | add bit more TODO
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2020-06-03 |
Luke Kenneth Casson... | update submodule for ISA tables
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2020-06-03 |
Luke Kenneth Casson... | convenience rename for spr pipe_data.py, consistent...
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2020-06-03 |
Luke Kenneth Casson... | add more TODOs
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2020-06-03 |
Luke Kenneth Casson... | add some more constants and ref to POWER9 pdf
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2020-06-03 |
Luke Kenneth Casson... | add an if for OP_MTMSR and some comments
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2020-06-02 |
Luke Kenneth Casson... | argh - bad hack, detecting when there are no registers...
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2020-06-02 |
Luke Kenneth Casson... | take out unneeded code, add Settle() to see if it helps...
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2020-06-02 |
Luke Kenneth Casson... | add lk field to DecodeOut2
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2020-06-02 |
Luke Kenneth Casson... | move setting cia input to branch from get_cu_inputs...
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2020-06-02 |
Luke Kenneth Casson... | hooray, get_cu_inputs now common to both types of tests
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2020-06-02 |
Luke Kenneth Casson... | oooo very annoying. there does not appear to be any...
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2020-06-02 |
Luke Kenneth Casson... | add get_inputs function to branch test_pipe_caller
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2020-06-02 |
Luke Kenneth Casson... | remove unneeded variable
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2020-06-02 |
Luke Kenneth Casson... | Revert "ok ok - for OP_BCREG put CTR in spr2 as well"
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2020-06-02 |
Luke Kenneth Casson... | ok ok - for OP_BCREG put CTR in spr2 as well
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2020-06-02 |
Luke Kenneth Casson... | set up CTR and LR only on BCREG when needed
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2020-06-02 |
Luke Kenneth Casson... | decode fast spr for OP_BCREG CTR, TAR and LR
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2020-06-02 |
Luke Kenneth Casson... | add TODO comments for read_fast1/2
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2020-06-02 |
Luke Kenneth Casson... | argh overlapping commits on submodule (rebase did not...
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2020-06-02 |
Luke Kenneth Casson... | debugging branch fast registers
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2020-06-02 |
Luke Kenneth Casson... | add comment about fast1 and fast2 in branch test_pipe_caller
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2020-06-02 |
Luke Kenneth Casson... | add regspecmap function to PowerDecode2
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2020-06-02 |
Luke Kenneth Casson... | move regspec function to separate module
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2020-06-02 |
Luke Kenneth Casson... | add in fast regs support in decoder and into regspec_decode
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2020-06-02 |
Luke Kenneth Casson... | add 2nd write-reg for LD/ST Update mode
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2020-06-02 |
Luke Kenneth Casson... | add write-regs encoding to regspec decoder
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2020-06-02 |
Luke Kenneth Casson... | add read-write register numbering detection
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2020-06-02 |
Luke Kenneth Casson... | whoops cut/paste error, creating write_ports not read_ports
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2020-06-02 |
Luke Kenneth Casson... | whoops syntax error
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2020-06-02 |
Luke Kenneth Casson... | add function expressing the relationship between regspecs...
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2020-06-02 |
Luke Kenneth Casson... | whitespace
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commit | commitdiff | tree |
2020-06-02 |
Luke Kenneth Casson... | rename regspecs to give a consistent naming scheme
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2020-06-02 |
Luke Kenneth Casson... | add MSR constants, TODO translated
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2020-06-02 |
Luke Kenneth Casson... | add TODO comments from microwatt source code
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2020-06-01 |
Luke Kenneth Casson... | remove reading port 3 for CR pipeline. RS moved to...
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2020-06-01 |
Luke Kenneth Casson... | okaaay add a "rdflags" function which obtains the yes...
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2020-06-01 |
Luke Kenneth Casson... | add test_bc_reg (fails)
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2020-06-01 |
Luke Kenneth Casson... | remove unneeded fields from Decode2Execute1Type
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2020-06-01 |
Luke Kenneth Casson... | more unneeded fields from SR InputRecord
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2020-06-01 |
Luke Kenneth Casson... | remove data_len from SR input record
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2020-06-01 |
Luke Kenneth Casson... | remove zero/invert from ShiftRot Input Record
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2020-06-01 |
Luke Kenneth Casson... | add shift-rot input record and use it
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2020-06-01 |
Luke Kenneth Casson... | CompBROpSubset exists
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2020-06-01 |
Luke Kenneth Casson... | RS moved to port 1 (from port 3), remove need in ALU...
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2020-06-01 |
Luke Kenneth Casson... | remove use of reg3 in logical pipeline: CSV files moved...
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2020-06-01 |
Luke Kenneth Casson... | rotator carry is set into both XER CA and CA32 fields
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2020-06-01 |
Luke Kenneth Casson... | comment out rlwinm. for now
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2020-06-01 |
Luke Kenneth Casson... | argh - need to zero the src_i input after "Read" is...
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2020-06-01 |
Luke Kenneth Casson... | put RB in 2nd position (matching immediate) in ShiftRot...
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2020-06-01 |
Luke Kenneth Casson... | sigh - another instance where write-mask needed to...
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2020-06-01 |
Luke Kenneth Casson... | remove xer so/ov, swap rs/rb to correct(?) order in...
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2020-06-01 |
Luke Kenneth Casson... | add rlwinm. test instruction (sets CR0)
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2020-06-01 |
Luke Kenneth Casson... | remove duplicate signal
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2020-06-01 |
Luke Kenneth Casson... | allow ALU / Logical ops to select RS as 1st operand
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2020-06-01 |
Luke Kenneth Casson... | allow M*-Form shiftrot to swap RS/RB back to consistent...
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2020-06-01 |
Luke Kenneth Casson... | add first version of ShiftRot CompUnit test
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2020-06-01 |
Luke Kenneth Casson... | shiftrot uses LogicalOutputData not ALUOutputData
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2020-06-01 |
Luke Kenneth Casson... | add assertions for branch compunit output
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2020-06-01 |
Luke Kenneth Casson... | invert SPR1/2 in branch output data
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2020-06-01 |
Luke Kenneth Casson... | decode SPRs for branch
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