| 2021-12-18 |
Luke Kenneth Casson... | add icache/dcache/mmu unit test for TestIssuer
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | get instructions to re-run in issuer after I-Cache...
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | forgot to connect up I-Cache to MMU
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | move connection of bus.stall in icache.py,
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | tidyup
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commit | commitdiff | tree |
| 2021-12-18 |
Luke Kenneth Casson... | tlb_req_index is TLB_BITS long not TLB_SIZE
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commit | commitdiff | tree |
| 2021-12-16 |
Luke Kenneth Casson... | whoops, a Simulation bug, dcache bus ack Signal needed...
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commit | commitdiff | tree |
| 2021-12-16 |
Luke Kenneth Casson... | give names to MMU records
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commit | commitdiff | tree |
| 2021-12-16 |
Luke Kenneth Casson... | set_mmu_spr was using the slow-SPR index for the regfile
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commit | commitdiff | tree |
| 2021-12-16 |
Luke Kenneth Casson... | whoops remove duplicate code (cut/paste error) no harm...
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | remove more unneeded code
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | read MSR.PR and MSR.DR and update ICache priv/virt...
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | remove more of SVP64 from TestIssuerInternalInOrder
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | remove update of pc, msr and svstate from TestIssuerInOrder
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | move update of pc, msr and svstate into TestIssuerBase
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | comment-out TestIssuerInternalInorder for now
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | move alternative TestIssuerInternalInOrder to new file
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | split out common elaboratable code from TestIssuer,
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | big split-out of common functions in TestIssuer to...
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | simplifying / tidyup of TestIssuer to get CoreState
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | sort out MSR, read/write in same way as PC/SVSTATE...
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | whoops accidentally commented out setup of instructions
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commit | commitdiff | tree |
| 2021-12-15 |
Luke Kenneth Casson... | get fetch_failed working with no MMU
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commit | commitdiff | tree |
| 2021-12-14 |
Luke Kenneth Casson... | trying to get TestIssuer FSM to respond correctly to...
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commit | commitdiff | tree |
| 2021-12-14 |
Luke Kenneth Casson... | get OP_FETCH_FAILED to respond/return an exception...
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commit | commitdiff | tree |
| 2021-12-14 |
Luke Kenneth Casson... | update wb_get memory with instructions if required
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commit | commitdiff | tree |
| 2021-12-14 |
Luke Kenneth Casson... | MMU LOOKUP for fetch failed, priv mode is inversion...
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commit | commitdiff | tree |
| 2021-12-14 |
Luke Kenneth Casson... | link MSR.PR into MMU FSM OP_FETCH_FAILED
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | return temporarily to older version of pinmux submodule
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | request a flush of icache to clear the instruction...
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | fix test_loadstore1.py with MSR=PR/DR
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | set pr=0 because privileged mode is pr=0 not pr=1
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | add in missing MSRSpec import
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | commented-out code
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | fix up pr/dr/sf in PortInterfaceBase
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | pass in new MSRSpec to test_loadstore1.py not msr_pr=1
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | convert PortInterfaceBase to pass msr not msr_pr
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | convert LoadStore1 to new msr.pr/dr/sf
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | add msr to MMU Op Subset record
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | still have to import MSRSpec
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | connect up PortInterface priv_mode, virt_mode and mode_32bit
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | construct an MSRSpec in PortInterfaceBase (not used...
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | whoops wrong variable names
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | rename msr_pr to priv_mode in LDSTCompUnit
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | TODO comments about using MSRspec
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commit | commitdiff | tree |
| 2021-12-13 |
Luke Kenneth Casson... | change PortInterface naming to msr not msr_pr in set_wr_addr
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | set and reset instruction fault so it does not occur...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | when an exception happens, if it is a fetch_failed...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | delay MMU LOOKUP done by one clock so that the exception...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | bring MMU exception out where AllFunctionUnits (and...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | bring exception out from MMU FSM, correct "done"
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | add LDSTException output to MMU
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | drat, a test inverting the instruction made it into...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | starting to hack in fetch failed (including OP_FETCH_FAILED)
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | print debugs established that when a wb_get memory...
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | set fetch_failed into PowerDecoder2 combinatorially
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commit | commitdiff | tree |
| 2021-12-12 |
Luke Kenneth Casson... | in a terrible botched way, get at I-Cache and set it up
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | fix bug in unit test, forgot that wb_get mem dict is...
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | get FetchUnitInterface I-Cache test working (sort-of)
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | comment out broken test
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | whoops forgot to add pspec
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | add start of test_loadstore1_ifetch_unit_interface()
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | connect up I-Cache to FetchUnitInterface
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commit | commitdiff | tree |
| 2021-12-11 |
Luke Kenneth Casson... | add new ConfigFetchUnit option "mmu_cache_wb" which...
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commit | commitdiff | tree |
| 2021-12-09 |
Luke Kenneth Casson... | add some examination of the failed-fetched instruction
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commit | commitdiff | tree |
| 2021-12-09 |
Luke Kenneth Casson... | add some debug string info to gtkwave
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commit | commitdiff | tree |
| 2021-12-09 |
Luke Kenneth Casson... | add I-Cache to FSM local variables
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commit | commitdiff | tree |
| 2021-12-09 |
Luke Kenneth Casson... | wire fetch_failed from I-Cache to PowerDecoder2
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commit | commitdiff | tree |
| 2021-12-09 |
Luke Kenneth Casson... | make icache accessible to core, working back to TestIssuer
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commit | commitdiff | tree |
| 2021-12-09 |
Luke Kenneth Casson... | include SPR.TB in SPR FU
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | got fed up of staring at magic constants in the MMU
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | add special pagetable to ifetch_invalid with execute...
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | do not try priv_mode on the instruction fetch (not...
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | add an example pagetable where executable permission...
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | check that no exception occurs in the virtual-memory...
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | add OP_FETCH_FAILED to MMU Function Unit
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | make LoadStore1 intsr_fault a "captured flag" - strictly...
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | remove MSR and add CIA to MMU Input Record
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | add instr_fault to LoadStore1 FSM
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commit | commitdiff | tree |
| 2021-12-08 |
Luke Kenneth Casson... | add new PortInterfaceBase external_busy() option
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | complete the i-cache fetch through the MMU, including...
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | set separate "iside" signal in LoadStore1 to not confuse it
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | start extending icache loadstore test
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | whoops another serious error in the CacheTagArray
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | add first i-cache fetch (non-virtual), no MMU lookup...
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | code-comments
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | add in I-Cache into LoadStore1 - presently unused ...
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | add discussion links and bugreport
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | invert mmureq statements
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | submodule tidyup
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | tidyup, comments
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commit | commitdiff | tree |
| 2021-12-07 |
Luke Kenneth Casson... | debug print
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | another major bug, CacheTagArray valid was only 1 bit...
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | tidyup: move hit_set to DCachePendingHit in dcache.py
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | dcache.py tidyup
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | rename dtlb to dtlb_valid and tidyup
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | convert TLBArray to TLBValidArray
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | convert DTLBUpdate to use a pair of Memorys
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | more signals local to DTLBUpdate
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commit | commitdiff | tree |
| 2021-12-06 |
Luke Kenneth Casson... | more signals local to DTLBUpdate
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commit | commitdiff | tree |
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