soc.git
2020-05-28 Michael NolanFix test_isel to properly examine registers
2020-05-28 Tobias Platenunittest for DataMerger
2020-05-28 Tobias Platenmore fixes for DataMerger
2020-05-28 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-28 Tobias Platenfixes for l0_cache.py
2020-05-28 Luke Kenneth... debug-print rd/wr rel in test_alu_compunit
2020-05-28 Luke Kenneth... add quick test of 3-operand DummyALU in MultiCompALU
2020-05-28 Luke Kenneth... add 3rd parameter to DummyALU
2020-05-28 Luke Kenneth... debugging test_alu_compunit.py
2020-05-28 Luke Kenneth... start on a compunit ALU test
2020-05-28 Luke Kenneth... update comment
2020-05-28 Luke Kenneth... remove trick of not setting SO
2020-05-28 Cesar StraussCheck that rd rises after issue_i, unless it's immediate
2020-05-28 Luke Kenneth... hmm....
2020-05-28 colepoirierAdd sync Assert for _wrports 'wen' signal in proof_regf...
2020-05-28 Cesar StraussStore and present parameters together with issue_i
2020-05-27 Luke Kenneth... do not use range(0, x) - just range(x)
2020-05-27 Luke Kenneth... remove write-block on register zero
2020-05-27 Luke Kenneth... code-morph, add TODO on OP_RFID, OP_SC, OP_ADDPCIS
2020-05-27 colepoirierDerive proof_regfile Driver from regfile.Register(...
2020-05-27 colepoirierFix indentation of regfile/formal/proof_regfile.py
2020-05-27 colepoirierFirst commit of proof of regfile, not working yet
2020-05-27 Luke Kenneth... add LD/ST pipe_data
2020-05-27 Luke Kenneth... LogicalOutputData does not need XER.so
2020-05-27 Luke Kenneth... comments
2020-05-27 Luke Kenneth... remove XER.ca from logical Input Data - not needed
2020-05-27 Luke Kenneth... cleanup logical main proof
2020-05-27 Luke Kenneth... check cr0, ov and ca ok signals in ALU main_stage proof
2020-05-27 Luke Kenneth... add carry-out, overflow and cr0 ok setting in ALU main_...
2020-05-27 Luke Kenneth... add SRR0 to TrapInputData
2020-05-27 Luke Kenneth... add links to bugreports into ALu formal proof as well
2020-05-27 Luke Kenneth... add links to bugreports into alu output stage proof
2020-05-27 Luke Kenneth... check reg output Data.ok in shift_rot formal proof
2020-05-27 Luke Kenneth... rename CROutputData.cr_o to just CROutputData.cr
2020-05-27 Luke Kenneth... test Data.ok for cr output and full cr output
2020-05-27 Luke Kenneth... assign and test on Data, TODO add Data.ok checking...
2020-05-27 Michael NolanFix bug in alu main stage proof
2020-05-27 Cesar StraussMove test case parameters to an "operation" member...
2020-05-27 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-27 Tobias Platenelaborate function for DataMerger
2020-05-27 Cesar StraussRemove the monitor process
2020-05-27 Luke Kenneth... make power function unit enum bitmasked
2020-05-27 Luke Kenneth... add extra INT regs port for now, add Fast Regfile
2020-05-27 Luke Kenneth... added XER and CR regfiles, using new VirtualRegPort
2020-05-26 Luke Kenneth... check assertions
2020-05-26 Luke Kenneth... make read/write regs properly internal
2020-05-26 Luke Kenneth... add VirtualRegPort test, seems to demonstrate it working
2020-05-26 Luke Kenneth... remove sync (not needed)
2020-05-26 Luke Kenneth... get score6600_multi.py working again
2020-05-26 Luke Kenneth... redo focus of virtual reg port to do only full datawidt...
2020-05-26 Michael NolanAdd extras from bottom of the file
2020-05-26 Michael NolanRewrite proof to be more in line with what appears...
2020-05-26 Luke Kenneth... sort-of (maybe) implemented a virtual port on top of...
2020-05-26 Luke Kenneth... try new variant of VirtualRegFile
2020-05-26 Luke Kenneth... use nmutil treereduce
2020-05-26 Luke Kenneth... continue virtual regfile port
2020-05-26 Luke Kenneth... whitespace, add commentary
2020-05-26 colepoirierFirst attempt at implementing block access rd and wr...
2020-05-25 Cesar StraussCheck that busy_o doesn't rise on its own
2020-05-25 Cesar StraussImplement the issue_i/busy_o protocol check.
2020-05-25 Cesar StraussMove process list to CompUnitParallelTest
2020-05-25 Michael NolanCorrect polarity of shadow signal
2020-05-25 Luke Kenneth... document shadown inversion
2020-05-25 Michael NolanAdd link to compunit wiki page
2020-05-25 Michael NolanCorrect property numbers, add assertions about busy
2020-05-25 Luke Kenneth... update comments on compalu_multi.py
2020-05-25 Michael NolanAdd assertions about go_wr and wr_rel
2020-05-25 Michael NolanMinor cleanup of comments
2020-05-25 Michael NolanMinor changes to alu_hier.py to allow it to be used...
2020-05-25 Michael NolanBegin working on proof for compunit/fu
2020-05-25 Luke Kenneth... add some more stub comments
2020-05-25 Luke Kenneth... yield blank so test passes
2020-05-25 Luke Kenneth... add stubs
2020-05-25 Luke Kenneth... add comments
2020-05-25 Cesar StraussFix detection of busy_o inside the monitor process
2020-05-25 Cesar StraussProof of concept of a parallel test
2020-05-25 Tobias Platenfix own copy/paste error
2020-05-25 Tobias Platenwhitespace fix in docstring
2020-05-25 Luke Kenneth... correct links in regfile docstring
2020-05-25 Luke Kenneth... document regfiles
2020-05-25 Luke Kenneth... argh! frickin MACos terminal expanded out to 86x30...
2020-05-25 Luke Kenneth... add docstring
2020-05-25 Luke Kenneth... add INT, SPR and CR regfiles
2020-05-25 Tobias Platenrefactoring (see #216 Comment 43)
2020-05-25 Tobias Platenwhitespace changes
2020-05-25 Luke Kenneth... quick addition of zero+immed test to LDSTCompUnit
2020-05-25 Luke Kenneth... must not do rd-req checking when both imm and zero...
2020-05-25 Tobias Platenimplement DataMerger interface
2020-05-25 Luke Kenneth... add zero immed on LDST, untested
2020-05-25 Luke Kenneth... comment out invalid test
2020-05-25 Luke Kenneth... lots of greater than 80 chars
2020-05-25 Luke Kenneth... switch out req rel if immediate enabled
2020-05-25 Cesar StraussShow oper_r and oper_i in the signal list, in simulation
2020-05-25 Luke Kenneth... mention zeroing
2020-05-25 Luke Kenneth... add links to pseudocode
2020-05-24 Luke Kenneth... spelling
2020-05-24 Luke Kenneth... spelling
2020-05-24 Luke Kenneth... add comments for SPR pipe_data
2020-05-24 Luke Kenneth... add SPR pipe_data.py
2020-05-24 Luke Kenneth... over 80 char limit
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