| 2022-06-26 |
Luke Kenneth... | store KAIVB SPR 850 in TRAP Pipeline |
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| 2022-06-26 |
Luke Kenneth... | reduce icache/dcache TLB sizes |
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| 2022-06-26 |
Luke Kenneth... | update trap test_pipe_caller.py to use up-to-date test... |
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| 2022-06-26 |
Luke Kenneth... | missing module argument to TestRunner execute |
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| 2022-06-26 |
Luke Kenneth... | convert trap test_pipe_caller.py to consistent format |
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| 2022-05-23 |
Andrey Miroshnikov | Change usage of WB sel for individual control |
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| 2022-05-01 |
Luke Kenneth... | split out front of div into separate stage, still too... |
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| 2022-04-30 |
Luke Kenneth... | add missing module |
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| 2022-04-30 |
Luke Kenneth... | split off CR0/XER production in DIV Function Unit into... |
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| 2022-04-30 |
Luke Kenneth... | clear out DEC in core.cur_state.dec due to spurious... |
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| 2022-04-30 |
Cesar Strauss | Implement transparent read port option on the XOR wrapp... |
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| 2022-04-29 |
Jacob Lifshay | fix waay-too-precise error requirements |
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| 2022-04-29 |
Luke Kenneth... | add option to set small cache sizes in |
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| 2022-04-29 |
Jacob Lifshay | add comment |
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| 2022-04-29 |
Jacob Lifshay | fix so HDL works for 5, 8, 16, 32, and 64-bits. |
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| 2022-04-29 |
Jacob Lifshay | HDL works for io_width=5 |
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| 2022-04-28 |
Cesar Strauss | Test simultaneous transparent reads and partial writes |
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| 2022-04-28 |
Jacob Lifshay | add docs for clz |
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| 2022-04-28 |
Jacob Lifshay | add WIP HDL version of goldschmidt division -- it's... |
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| 2022-04-28 |
Luke Kenneth... | notes added to setup.py - absolute paranoia is needed on |
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| 2022-04-28 |
Jacob Lifshay | move GoldschmidtDivState |
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| 2022-04-28 |
Jacob Lifshay | add FIXME comments |
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| 2022-04-28 |
Jacob Lifshay | add the goldschmidt sqrt/rsqrt algorithm, still need... |
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| 2022-04-27 |
Jacob Lifshay | switch cached-property dependency to using libre-soc... |
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| 2022-04-27 |
Jacob Lifshay | improved goldschmidt division algorithm parameter optim... |
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| 2022-04-27 |
Jacob Lifshay | split out non-derived params into separate class withou... |
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| 2022-04-27 |
Jacob Lifshay | split out n_hat as separate property |
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| 2022-04-27 |
Jacob Lifshay | add default_cost_fn |
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| 2022-04-27 |
Jacob Lifshay | move GoldschmidtDivParams.get to bottom of class |
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| 2022-04-27 |
Jacob Lifshay | rename _goldschmidt_div_ops to GoldschmidtDivState... |
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| 2022-04-26 |
Jacob Lifshay | goldschmidt division works! still needs better paramete... |
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| 2022-04-26 |
Jacob Lifshay | fix goofed __init__.py file name |
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| 2022-04-25 |
Jacob Lifshay | working on goldschmidt_div_sqrt.py |
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| 2022-04-25 |
Jacob Lifshay | add cached_property dependency |
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| 2022-04-23 |
Jacob Lifshay | working on goldschmidt division algorithm |
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| 2022-04-22 |
Luke Kenneth... | whitespace |
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| 2022-04-22 |
Jacob Lifshay | add WIP goldschmidt division algorithm |
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| 2022-04-17 |
Cesar Strauss | Implement a 1W/1R register file, XOR style |
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| 2022-04-17 |
Cesar Strauss | Formal proof of pseudo 1W/2R SRAM |
commit | commitdiff | tree |
| 2022-04-17 |
Cesar Strauss | Add transparent option for the full read port |
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| 2022-04-17 |
Cesar Strauss | Implement a pseudo 1W/2R memory |
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| 2022-04-16 |
Luke Kenneth... | reduce dcache/icache number of ways, to fit into ECP5... |
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| 2022-04-16 |
Tobias Platen | part two of issuer_fix: read pspec.microwatt_old and... |
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| 2022-04-16 |
Cesar Strauss | Check non-transparent 1W/1R SRAM wrapper |
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| 2022-04-16 |
Cesar Strauss | Enable read port for non-transparent memories |
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| 2022-04-16 |
Tobias Platen | Merge ssh://git.libre-riscv.org:922/soc |
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| 2022-04-16 |
Tobias Platen | part one of issuer_fix: add parameter to issuer_verilog.py |
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| 2022-04-16 |
Cesar Strauss | Add port declarations to the SRAM wrappers |
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| 2022-04-16 |
Cesar Strauss | Change write lane signal from one-hot to binary |
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| 2022-04-16 |
Luke Kenneth... | whoops, WBASyncBridge ack signal not wired up! |
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| 2022-04-16 |
Luke Kenneth... | select width is data_width // data granularity. |
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| 2022-04-16 |
Cesar Strauss | Synchronize LVT state, completing the induction proof |
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| 2022-04-16 |
Cesar Strauss | Sync proof state with downstream memories |
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| 2022-04-16 |
Luke Kenneth... | put the old microwatt compatibility back |
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| 2022-04-16 |
Luke Kenneth... | blegh. |
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| 2022-04-15 |
Cesar Strauss | Complete moving the induction support into the DUT |
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| 2022-04-15 |
Cesar Strauss | Fix incorrect signal widths |
commit | commitdiff | tree |
| 2022-04-15 |
Cesar Strauss | Move part of formal proof to the implementation |
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| 2022-04-14 |
Luke Kenneth... | add option Spec to XICS ICP/ICS to be able to activate... |
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| 2022-04-14 |
Luke Kenneth... | move IRQLine out because that makes soc dependent on... |
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| 2022-04-14 |
Luke Kenneth... | 80 char limit, remove creation of stall from ack/cyc... |
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| 2022-04-14 |
Raptor Engineering... | wb_async: Allow different feature fields for master... |
commit | commitdiff | tree |
| 2022-04-14 |
Raptor Engineering... | Add separate memory clock register to SYSCON |
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| 2022-04-12 |
Tobias Platen | issuer.py: add microwatt_old and microwatt_debug options |
commit | commitdiff | tree |
| 2022-04-11 |
Raptor Engineering... | Separate core and nest clocks in Microwatt SYSCON |
commit | commitdiff | tree |
| 2022-04-11 |
Raptor Engineering... | Add initial wrapper for Wishbone asynchronous bridge... |
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| 2022-04-10 |
Cesar Strauss | Begin a formal proof of the LVT-based 1W/1R wrapper |
commit | commitdiff | tree |
| 2022-04-10 |
Cesar Strauss | Implement 1W/1R with a transparent (or not) read port. |
commit | commitdiff | tree |
| 2022-04-10 |
Cesar Strauss | Implement a true 1W/1R memory from 1RW blocks |
commit | commitdiff | tree |
| 2022-04-09 |
Luke Kenneth... | add a new make target for setting coldboot firmware... |
commit | commitdiff | tree |
| 2022-04-08 |
Luke Kenneth... | syntax error |
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| 2022-04-08 |
Luke Kenneth... | add dram to SysCon |
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| 2022-04-08 |
Luke Kenneth... | add SPI offset to microwatt syscon |
commit | commitdiff | tree |
| 2022-04-06 |
Luke Kenneth... | only add clock-settings on ECP5 due to special SPI... |
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| 2022-04-04 |
Luke Kenneth... | add tempfile to uart16550 wrapper which defines DATA_BU... |
commit | commitdiff | tree |
| 2022-04-04 |
Luke Kenneth... | disable sphinx verilg-diagrams for now |
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| 2022-04-04 |
Luke Kenneth... | allow direction-setting on each of dq0-3 in Tercel... |
commit | commitdiff | tree |
| 2022-04-03 |
Luke Kenneth... | cant stand the practice of putting docstrings *after... |
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| 2022-04-03 |
Cesar Strauss | Extend the proof to a non-transparent port |
commit | commitdiff | tree |
| 2022-04-03 |
Cesar Strauss | Run formal proof on both types (even/odd) of phased... |
commit | commitdiff | tree |
| 2022-04-03 |
Cesar Strauss | Complete the formal proof of the pseudo dual port SRAM |
commit | commitdiff | tree |
| 2022-04-03 |
Cesar Strauss | Implement a debug port on the pseudo 1W/1R SRAM |
commit | commitdiff | tree |
| 2022-04-03 |
Cesar Strauss | Formal proof of the phased write dual port memory wrapper |
commit | commitdiff | tree |
| 2022-04-03 |
Luke Kenneth... | correct default to zero string not zero int |
commit | commitdiff | tree |
| 2022-04-03 |
Luke Kenneth... | add alternative pc_reset argument to issuer_verilog.py |
commit | commitdiff | tree |
| 2022-04-03 |
Luke Kenneth... | fix some of instantiation errors in opencores_ethmac.py |
commit | commitdiff | tree |
| 2022-04-02 |
Raptor Engineering... | Fix opencores EthMAC module wiring |
commit | commitdiff | tree |
| 2022-04-02 |
Cesar Strauss | Implement transparent read ports on the phased write... |
commit | commitdiff | tree |
| 2022-04-02 |
Cesar Strauss | Implement and test a "phased write port" memory |
commit | commitdiff | tree |
| 2022-03-31 |
Luke Kenneth... | invert cs_n pin in Tercel |
commit | commitdiff | tree |
| 2022-03-30 |
Luke Kenneth... | nope, default features in Tercel WB Buses need to not... |
commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth... | add bus.err to list of default Wishbone signals in... |
commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth... | byte-reverse Tercel read/write data and config bus... |
commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth... | set clock freq Constant length to 32-bit in Tercel. |
commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth... | self.specials does not exist, Instances must be added... |
commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth... | more sorting out wishbone names in Tercel |
commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth... | fix names of Instance signals in Tercel |
commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth... | sort out variable names in Tercel |
commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth... | self.comb does not exist, comb is a local temp-var... |
commit | commitdiff | tree |
| 2022-03-29 |
Luke Kenneth... | whitespace cleanup (80 char limit) |
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