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soc.git
2020-11-19
Cesar Strauss
Separate input and output ports by color
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2020-11-19
Cesar Strauss
Explain the test cases
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2020-11-18
Cesar Strauss
Separate individual traces for each rel_o/go_i port
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2020-11-17
Tobias Platen
testcase for dcbz
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2020-11-16
Cesar Strauss
Add a transaction counter to producers and consumers
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2020-11-16
Tobias Platen
add class LoadStore1(PortInterfaceBase)
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2020-11-15
Cesar Strauss
Implement ResultConsumer and port the Shifter unit...
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2020-11-14
Cesar Strauss
Move the DUT driver to within the test case process
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2020-11-14
Cesar Strauss
Fix and enable the regspec test for the Shifter
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2020-11-14
Luke Kenneth...
sigh, direction wrong in IOtypes litex core
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2020-11-13
Luke Kenneth...
reduce number of nc in ls180 to 24
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2020-11-13
Luke Kenneth...
reduce clkcsel ls180 width (2 pins), rename pll_18...
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2020-11-13
Luke Kenneth...
rename and add pll lock signal to ls180
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2020-11-13
Luke Kenneth...
rename ls180 litex pll_48 output to pll_18
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2020-11-13
Luke Kenneth...
add enable/disable arguments (not ideal but it works...
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2020-11-13
Luke Kenneth...
remove io_in/out now it is not needed for niolib
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2020-11-11
Tobias Platen
dcbz and tlbie first test, still incomplete
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2020-11-11
Tobias Platen
fu/mmu/test/test_pipe_caller.py test case for mfspr
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2020-11-10
Luke Kenneth...
add build commands to Makefile for versa ecp5
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2020-11-10
Luke Kenneth...
submodule update
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2020-11-10
Luke Kenneth...
remove ClockSelect module, use DummyPLL
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2020-11-10
Luke Kenneth...
add separate DummyPLL module, according to API discussed at
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2020-11-08
Tobias Platen
mmu fsm testcase: add check_fsm_outputs based on functi...
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2020-11-08
Tobias Platen
Merge branch 'master' of ssh://git.libre-riscv.org...
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2020-11-08
Tobias Platen
mmu/fsm: test case for mtspr
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2020-11-07
Luke Kenneth...
update submodule
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2020-11-07
Tobias Platen
fixed a bug in src/soc/fu/mmu/fsm.py
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2020-11-06
Luke Kenneth...
sigh sorting out litex pin-connections to sdram
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2020-11-04
Luke Kenneth...
move back to 3.3v on X3 VERSA ECP5 connector
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2020-11-04
Tobias Platen
MMU: begin test case for 'dcbz'
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2020-11-03
Tobias Platen
fix broken unittest after installing power-instruction...
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2020-11-03
Luke Kenneth...
swap jtag pinorder to match ulx3s
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2020-11-03
Luke Kenneth...
change LVCMOS level on versa ecp5 jtag to 2.5v
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2020-11-01
Cesar Strauss
Add a check for liveness.
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2020-10-31
Cole Poirier
versa_ecp5.py add 4 arbitrarily assigned gpio pins...
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2020-10-31
Cesar Strauss
Check that the read and write counters differ at most...
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2020-10-31
Cesar Strauss
Remove stray comment
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2020-10-30
Luke Kenneth...
add JTAG extension to versa_ecp5 then we can use it
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2020-10-28
Cesar Strauss
Implement an operand producer that talks the rel_o...
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2020-10-24
Luke Kenneth...
submodule update
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2020-10-24
Cesar Strauss
Create a GTKWave document for the test ALU unit tests
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2020-10-22
Luke Kenneth...
add query about cross-domain on the JTAG enable of WB
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2020-10-22
Luke Kenneth...
add detection and disable of Instruction Wishbone based...
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2020-10-22
Luke Kenneth...
add detection and disable of LoadStore Wishbone based...
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2020-10-22
Luke Kenneth...
add JTAG enable/disable of wishbone to TestIssuer
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2020-10-22
Luke Kenneth...
add means to JTAG interface to enable/disable "stuff...
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2020-10-21
Cole Poirier
versa_ecp5 adds ability to build and load for ulx3s85f...
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2020-10-21
Luke Kenneth...
fix up asserts (check correct pads/cores)
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2020-10-20
Tobias Platen
s/alu/fsm/g
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2020-10-20
Tobias Platen
test case for FSMMMUStage
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2020-10-18
Cole Poirier
use random.seed to generate repro cases of the two...
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2020-10-16
Luke Kenneth...
experiment swapping dummy trap stage over to input
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2020-10-16
Luke Kenneth...
re-enable tests
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2020-10-16
Luke Kenneth...
manually run coresync clock for test issuer
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2020-10-16
Luke Kenneth...
set defaults in pspec
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2020-10-16
Luke Kenneth...
update submodule
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2020-10-16
Luke Kenneth...
add extra (test dummy stage in trap to see if combinato...
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2020-10-16
Luke Kenneth...
add LGPLv3+ notice and add copyright holders
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2020-10-15
Luke Kenneth...
add commented-out connection to JTAG in ECP5 litex
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2020-10-15
Luke Kenneth...
wrong pspec variable in selecting pll clock
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2020-10-15
Luke Kenneth...
sorting out missing clock somewhere
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2020-10-15
Luke Kenneth...
use "enable" and set default actions in getopt
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2020-10-15
Luke Kenneth...
add extra variant to litex core
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2020-10-15
Luke Kenneth...
syntax error
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2020-10-15
Luke Kenneth...
disable gpio in litex core
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2020-10-15
Luke Kenneth...
enable/disable litex irqs based on variant name
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2020-10-14
Cole Poirier
Makefile develop, when running setup.py develop specify...
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2020-10-14
Cole Poirier
issuer_verilog.py update to use commandline args using...
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2020-10-13
Cole Poirier
move pia from install_requires to test_requires
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2020-10-12
Cole Poirier
litex/florent/versa_ecp5.py add arg --fpga [versa_ecp5...
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2020-10-12
Cole Poirier
fix ModuleNotFound/Import errors found when running...
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2020-10-12
Tobias Platen
update gitlab ci
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2020-10-12
Cole Poirier
add tested working fpga compile/build/load file for...
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2020-10-11
Luke Kenneth...
add way to bypass PLL for ECP5 and sim
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2020-10-11
Luke Kenneth...
comment out XICS/GPIO interrupt test, causes ECP5 litex...
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2020-10-11
Luke Kenneth...
record commands for building ECP5
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2020-10-11
Luke Kenneth...
litex sim.py operational
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2020-10-10
Cole Poirier
florent/versa_ecp5.py remove uneccessary imports, speci...
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2020-10-10
Luke Kenneth...
add debug start/stop to firmware_upload script
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2020-10-10
Luke Kenneth...
add DMI status / reset to firmware upload script
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2020-10-10
Luke Kenneth...
add first version of firmware uploader
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2020-10-09
Jacob Lifshay
update submodule
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2020-10-09
Jacob Lifshay
update submodule
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2020-10-09
Luke Kenneth...
use libresoc version of c4m-jtag repo
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2020-10-09
Luke Kenneth...
submodule update
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2020-10-09
Luke Kenneth...
drop in "undefined" function into ISAcaller namespace
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2020-10-09
Luke Kenneth...
rename undef to undefined (preserving the fact that...
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2020-10-09
Luke Kenneth...
missing yields in JTAG pads test to allow settling
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2020-10-09
Jacob Lifshay
finish converting mul tests to use common code
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2020-10-09
Jacob Lifshay
working on splitting out common mul pipe test code
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2020-10-09
Jacob Lifshay
add carry handling to pia_res_to_output
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2020-10-09
Jacob Lifshay
move pia_res_to_output to common test helpers
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2020-10-09
Jacob Lifshay
move mul pipe ilang test to separate file
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2020-10-09
Jacob Lifshay
add undef()
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2020-10-09
Jacob Lifshay
update submodule
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2020-10-08
Jacob Lifshay
update submodule
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2020-10-08
Luke Kenneth...
missing yields in JTAG pads test to allow settling
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2020-10-08
Luke Kenneth...
minor icache cleanup
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2020-10-08
Cole Poirier
second attempt at https://bugs.libre-soc.org/show_bug...
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2020-10-08
Cole Poirier
remove singleton dict per https://bugs.libre-soc.org...
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