soc.git
2021-09-09 klehmanHDL int reg added
2021-09-09 klehmanmore sim class registers add
2021-09-08 Cesar StraussMonitor exceptions, re-decoding the instruction in...
2021-09-08 klehmaninitial commit of sim state class
2021-09-08 Cesar StraussMonitor the exception input to PowerDecoder2
2021-09-08 Cesar StraussRemove default argument for dict.get()
2021-09-07 Luke Kenneth... fun fixing of get_core_hdl_regs, "yield from"
2021-09-07 Luke Kenneth... move functions to above where they are called
2021-09-07 klehmanbreakout of register collection and compare
2021-09-07 Cesar StraussFix typo.
2021-09-07 Luke Kenneth... add TODO code-comments
2021-09-07 Luke Kenneth... whitespace, add bug ref number to test API
2021-09-03 Luke Kenneth... another batch of ready/valid i/o prefix-suffix swaps
2021-08-31 Luke Kenneth... anooother valid_o to convert to o_valid
2021-08-31 Luke Kenneth... update ready/valid in shift_rot test_pipe_caller
2021-08-31 Jacob Lifshayfix test_all_values_covered, missed import when moving...
2021-08-30 Luke Kenneth... update ready/valid i/o_ prefix in div test helper.py
2021-08-30 Luke Kenneth... fix ready/valid i/o prefix in ALU test
2021-08-30 Luke Kenneth... fix CR tests valid/ready naming
2021-08-30 Luke Kenneth... missed valid/ready_i/o to o/i_ conversion
2021-08-30 Luke Kenneth... missed valid/ready_i/o to o/i_ conversion
2021-08-29 Luke Kenneth... unnecessary signal rename ivalid_i to ii_valid (reverting)
2021-08-24 Luke Kenneth... replace data_o with o_data and data_i with i_data as...
2021-08-24 Luke Kenneth... big rename, global/search/replace of ready_o with o_rea...
2021-08-22 Luke Kenneth... remove svanalysis from Makefile, it is now part of...
2021-08-17 Tobias Platenfix "link addr-go direct to rel"
2021-08-17 Cesar StraussEnable LD/ST exception test case
2021-08-17 Cesar StraussClear operand latch on a terminating condition
2021-08-17 Cesar StraussAdd exc_o.happened to the conditions for terminating...
2021-08-17 Cesar StraussFix activation of cancel signal
2021-08-16 Cesar StraussAdjust PortInterface traces according to MMU option
2021-08-16 Tobias Platenfix renamed symbols
2021-08-16 Tobias Platenadd WIP DCBZTestCase
2021-08-11 Jonathan NeuschäferGitLab-CI: Only run tests in src/
2021-08-01 Luke Kenneth... move unused directory out of src, to indicate "ignore...
2021-08-01 Jonathan Neuschäferimport setup_i_memory from soc.simple.test.test_runner
2021-08-01 Jonathan Neuschäfersoc.simple.test: Rename setup_test_memory to avoid...
2021-08-01 Jonathan NeuschäferRename test_dcache, which can't be invoked by test...
2021-08-01 Luke Kenneth... simulator/test_sim.py should not have been added
2021-07-31 Tobias Platenpartial fix for src/soc/experiment/compldst_multi.py
2021-07-30 Tobias Platenpartially fix unit test in compldst_multi.py
2021-07-26 Tobias Platencompldst_multi: add debug output for dcbz
2021-07-24 Tobias Platenadd test_issuer_dcache.py
2021-07-23 Tobias Platenldst: cleanup debug outputs
2021-07-23 Tobias Platentest_dcbz_pi.py: dcbz now working
2021-07-21 Tobias Platenrevert accidential delete in test_pi2ls.py causing...
2021-07-21 Tobias Platentest_dcbz_pi.py: do not use problem state
2021-07-21 Tobias Platenupdate pi_dcbz function
2021-07-19 Tobias Platensrc/soc/config/test/test_pi2ls.py: add more debug outputs
2021-07-19 Tobias Platentest_dcbz_pi.py: more work on unit test
2021-07-15 Luke Kenneth... update TestRunner, SVSTATE is now a class that inherits...
2021-07-14 Luke Kenneth... update SVSTATE to 64 bit length (fortunately very easy)
2021-07-14 Tobias Platenadd more debug outputs, pass dcbz to loadstore/dcache
2021-07-14 Tobias Platendcache: improve debug output
2021-07-12 Luke Kenneth... use standard create_pdecode in TestRunner
2021-07-12 Luke Kenneth... use default decoder, do not pass one in.
2021-07-11 Tobias Platenmore work on test_dcbz_pi.py
2021-07-11 Tobias Platenpass self.pi.is_dcbz to request
2021-07-11 Tobias Platenimplement pi_dcbz
2021-07-11 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2021-07-11 Tobias Platenadd test_dcbz_pi.py (skeleton only)
2021-07-10 Cesar StraussShow some usage of PortInterface in action
2021-07-10 Cesar StraussAdd new traces to the GTKWave document
2021-07-10 Cesar StraussAdd operand producers to the parallel LDST Compunit...
2021-07-10 Cesar StraussDetect unexpected operand fetches and produced results
2021-07-07 Cesar StraussStart of a GTKWave document for the LDST CompUnit paral...
2021-07-04 Cesar StraussBeginning of a class to make a parallel test case for...
2021-06-30 Tobias Platencut down on time by uncommenting data not needed, addin...
2021-06-28 Tobias Platenupdate ldst test case by adding precise timing
2021-06-24 Luke Kenneth... propagate new use_svp64_ldst_dec mode through TestCore...
2021-06-24 Luke Kenneth... add an explicit PowerDecoder.is_svp64_mode flag to...
2021-06-20 Tobias Platendcache: add debug output
2021-06-20 Tobias Platenupdate test_ldst_pi.py
2021-06-18 Tobias Platenuncomment test_dcache_random
2021-06-18 Tobias Platensrc/soc/fu/ldst/loadstore.py: keep data for the whole...
2021-06-14 Tobias Platenupdate testcase for ldst
2021-06-10 Luke Kenneth... whoops Popcount datalen too big (wasted bits). reduce
2021-06-09 Luke Kenneth... git submodule update
2021-06-09 Luke Kenneth... disconnect pll clock, connected in peripheral interconnect
2021-06-09 Luke Kenneth... add in/out of ref_clk and pllclk_clk when PLL enabled
2021-06-06 Cesar StraussStart a new self-contained test suite for LDSTCompUnit
2021-06-03 Luke Kenneth... comment out domains that have already been created
2021-06-03 Luke Kenneth... no, do not assign clock to clock!
2021-06-03 Luke Kenneth... rename ref to ref_v in PLL due to ref being a verilog...
2021-06-03 Luke Kenneth... sort out PLL domains but bypass PLL due to lack of...
2021-06-03 Luke Kenneth... use DomainRenamer on all sub-components of TestIssuer
2021-06-03 Luke Kenneth... make core_rst a member of TestIssuerInternal
2021-06-01 Tobias Platentest_ldst_pi.py: add new test case
2021-05-29 Tobias Platentest_ldst_pi.py: first version of test_dcache_random()
2021-05-29 Tobias Platentest_ldst_pi.py: more test_dcache_regression()
2021-05-27 Luke Kenneth... adjust PLL connections looking for coriolis2 issue
2021-05-27 Luke Kenneth... corrections on spblock ack
2021-05-27 Luke Kenneth... classic wishbone mode: must not do ack if already acked
2021-05-26 Luke Kenneth... arse. PLL test_issuer clk_sel_i accidentally only 1...
2021-05-26 Luke Kenneth... remove err feature from sram4k wb
2021-05-26 Luke Kenneth... add ldst PortInterface misalign unit test (underway)
2021-05-26 Luke Kenneth... rename PLL signals
2021-05-25 Tobias Platentest_ldst_pi.py: fix race condition causing early stop
2021-05-25 Tobias Platenwait_ldok: add debug output count
2021-05-24 Luke Kenneth... whoops sort out name of SPBlock RAM
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