soc.git
2020-10-24 Luke Kenneth... submodule update
2020-10-24 Cesar StraussCreate a GTKWave document for the test ALU unit tests
2020-10-22 Luke Kenneth... add query about cross-domain on the JTAG enable of WB
2020-10-22 Luke Kenneth... add detection and disable of Instruction Wishbone based...
2020-10-22 Luke Kenneth... add detection and disable of LoadStore Wishbone based...
2020-10-22 Luke Kenneth... add JTAG enable/disable of wishbone to TestIssuer
2020-10-22 Luke Kenneth... add means to JTAG interface to enable/disable "stuff...
2020-10-21 Cole Poirierversa_ecp5 adds ability to build and load for ulx3s85f...
2020-10-21 Luke Kenneth... fix up asserts (check correct pads/cores)
2020-10-20 Tobias Platens/alu/fsm/g
2020-10-20 Tobias Platentest case for FSMMMUStage
2020-10-18 Cole Poirieruse random.seed to generate repro cases of the two...
2020-10-16 Luke Kenneth... experiment swapping dummy trap stage over to input
2020-10-16 Luke Kenneth... re-enable tests
2020-10-16 Luke Kenneth... manually run coresync clock for test issuer
2020-10-16 Luke Kenneth... set defaults in pspec
2020-10-16 Luke Kenneth... update submodule
2020-10-16 Luke Kenneth... add extra (test dummy stage in trap to see if combinato...
2020-10-16 Luke Kenneth... add LGPLv3+ notice and add copyright holders
2020-10-15 Luke Kenneth... add commented-out connection to JTAG in ECP5 litex
2020-10-15 Luke Kenneth... wrong pspec variable in selecting pll clock
2020-10-15 Luke Kenneth... sorting out missing clock somewhere
2020-10-15 Luke Kenneth... use "enable" and set default actions in getopt
2020-10-15 Luke Kenneth... add extra variant to litex core
2020-10-15 Luke Kenneth... syntax error
2020-10-15 Luke Kenneth... disable gpio in litex core
2020-10-15 Luke Kenneth... enable/disable litex irqs based on variant name
2020-10-14 Cole PoirierMakefile develop, when running setup.py develop specify...
2020-10-14 Cole Poirierissuer_verilog.py update to use commandline args using...
2020-10-13 Cole Poiriermove pia from install_requires to test_requires
2020-10-12 Cole Poirierlitex/florent/versa_ecp5.py add arg --fpga [versa_ecp5...
2020-10-12 Cole Poirierfix ModuleNotFound/Import errors found when running...
2020-10-12 Tobias Platenupdate gitlab ci
2020-10-12 Cole Poirieradd tested working fpga compile/build/load file for...
2020-10-11 Luke Kenneth... add way to bypass PLL for ECP5 and sim
2020-10-11 Luke Kenneth... comment out XICS/GPIO interrupt test, causes ECP5 litex...
2020-10-11 Luke Kenneth... record commands for building ECP5
2020-10-11 Luke Kenneth... litex sim.py operational
2020-10-10 Cole Poirierflorent/versa_ecp5.py remove uneccessary imports, speci...
2020-10-10 Luke Kenneth... add debug start/stop to firmware_upload script
2020-10-10 Luke Kenneth... add DMI status / reset to firmware upload script
2020-10-10 Luke Kenneth... add first version of firmware uploader
2020-10-09 Jacob Lifshayupdate submodule
2020-10-09 Jacob Lifshayupdate submodule
2020-10-09 Luke Kenneth... use libresoc version of c4m-jtag repo
2020-10-09 Luke Kenneth... submodule update
2020-10-09 Luke Kenneth... drop in "undefined" function into ISAcaller namespace
2020-10-09 Luke Kenneth... rename undef to undefined (preserving the fact that...
2020-10-09 Luke Kenneth... missing yields in JTAG pads test to allow settling
2020-10-09 Jacob Lifshayfinish converting mul tests to use common code
2020-10-09 Jacob Lifshayworking on splitting out common mul pipe test code
2020-10-09 Jacob Lifshayadd carry handling to pia_res_to_output
2020-10-09 Jacob Lifshaymove pia_res_to_output to common test helpers
2020-10-09 Jacob Lifshaymove mul pipe ilang test to separate file
2020-10-09 Jacob Lifshayadd undef()
2020-10-09 Jacob Lifshayupdate submodule
2020-10-08 Jacob Lifshayupdate submodule
2020-10-08 Luke Kenneth... missing yields in JTAG pads test to allow settling
2020-10-08 Luke Kenneth... minor icache cleanup
2020-10-08 Cole Poiriersecond attempt at https://bugs.libre-soc.org/show_bug...
2020-10-08 Cole Poirierremove singleton dict per https://bugs.libre-soc.org...
2020-10-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-10-08 Tobias Platenadd WIP test_pipe_caller.py for mmu
2020-10-08 Luke Kenneth... add incoming PortInterface to be connected to LoadStore...
2020-10-08 Luke Kenneth... JTAG boundary scan test 1st attempt
2020-10-08 Luke Kenneth... rework jtag test to use JTAG class not DMITAP
2020-10-08 Luke Kenneth... split out jtag util functions to separate module
2020-10-08 Cole Poirierfirst attempt at 3) of
2020-10-08 Cole Poiriermodify wb_get per 1) of https://bugs.libre-soc.org...
2020-10-07 Tobias Platenconnect mmu_done, ldst_error, cache_paradox
2020-10-07 Luke Kenneth... missing invert_in field from shiftrot input record
2020-10-07 Luke Kenneth... git submodule update
2020-10-07 Luke Kenneth... reorder / reorganise reset signals slightly
2020-10-07 Jacob Lifshayfix div tests
2020-10-07 Jacob Lifshayupdate submodule
2020-10-07 Jacob LifshayFix forgotten test_pipe_caller changes from e0b4334c7d8...
2020-10-06 Tobias Platenremove redunant signals
2020-10-06 Luke Kenneth... update comments on pimem.py
2020-10-06 Tobias Platentest_mmu_dcache_pi.py
2020-10-06 Luke Kenneth... comments
2020-10-06 Luke Kenneth... add ports function to DummyPLL
2020-10-06 Luke Kenneth... use pdecode2.do not pdecode2.e in test_pipe_caller...
2020-10-06 Luke Kenneth... skip Decode2ToOperand from PowerDecodeSubset
2020-10-06 Luke Kenneth... comment SRR1 mem.exception
2020-10-06 Luke Kenneth... add SRR1 setting for LDST memory exception trap
2020-10-06 Luke Kenneth... passing LDSTException over to Trap Pipeline
2020-10-06 Luke Kenneth... add LDSTException decode/handling in PowerDecoder2
2020-10-06 Luke Kenneth... make LDSTException fields added from list of fieldnames
2020-10-06 Luke Kenneth... move LDSTException to mem_types
2020-10-06 Luke Kenneth... submodule update
2020-10-06 Luke Kenneth... add LDSTException to PortInterface
2020-10-06 Luke Kenneth... add sdr bypass routing via JTAG boundary scan
2020-10-06 Jacob Lifshayadd divde regression test
2020-10-06 Jacob Lifshayupdate submodule
2020-10-06 Jacob Lifshayadd moduw regression test
2020-10-06 Jacob Lifshayupdate submodule
2020-10-06 Jacob Lifshayadd workaround for nmigen bug #502
2020-10-06 Jacob Lifshayupdate submodule
2020-10-06 Jacob Lifshayadd modsw regression
2020-10-06 Jacob Lifshayadd test case for divweu regression
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