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soc.git
2020-08-25 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py rearrange, transform classes into functions... commit | commitdiff | tree
2020-08-25 Jacob Lifshayfix broken remainder for div FSM commit | commitdiff | tree
2020-08-25 Jacob Lifshayclean up formatting commit | commitdiff | tree
2020-08-25 Luke Kenneth... although shift-rot does not alter XER.so it still needs... commit | commitdiff | tree
2020-08-25 Luke Kenneth... add way to capture CR from DMI in litex sim commit | commitdiff | tree
2020-08-25 Luke Kenneth... add CR read to DMI interface commit | commitdiff | tree
2020-08-25 Luke Kenneth... shorten using temp vars commit | commitdiff | tree
2020-08-25 Luke Kenneth... add CR DMI interface commit | commitdiff | tree
2020-08-25 Luke Kenneth... add crxor unit test to qemu commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py fix whitespace, fomatting, syntax commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py fix formatting commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py move Reservation RecordObject to top of file commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py move RegStage1 RecordObject to top of file commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py move MemAccessRequest RecordObject to top... commit | commitdiff | tree
2020-08-25 Cole Poirierdcache.py move Stage0 RecordObject to top of file commit | commitdiff | tree
2020-08-24 Luke Kenneth... argh, reading regfile over DMI was overlapped and corru... commit | commitdiff | tree
2020-08-24 Luke Kenneth... add isel CR tests to run on qemu (confirmed working) commit | commitdiff | tree
2020-08-24 Tobias PlatenTestCachedMemoryPortInterface cleanup commit | commitdiff | tree
2020-08-24 Luke Kenneth... make it easier to select FSM/Pipe DIV unit commit | commitdiff | tree
2020-08-24 Luke Kenneth... fix *another* ld-update-related timing / FSM issue commit | commitdiff | tree
2020-08-24 Luke Kenneth... tidyup / shuffle after review commit | commitdiff | tree
2020-08-24 Luke Kenneth... remove default parameter commit | commitdiff | tree
2020-08-24 Luke Kenneth... "WAY" does not exist - range(NUM_WAYS) was intended commit | commitdiff | tree
2020-08-24 Luke Kenneth... use WAY_BITS in appropriate locations commit | commitdiff | tree
2020-08-24 Luke Kenneth... reminder that the license (reflecting what is in setup... commit | commitdiff | tree
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-24 Cole Poirierdcache.py commit first full tranlation pass, about... commit | commitdiff | tree
2020-08-23 Luke Kenneth... update copyright notices to include additional primary... commit | commitdiff | tree
2020-08-23 Luke Kenneth... add load algebraic immediate unit test commit | commitdiff | tree
2020-08-23 Luke Kenneth... add algebraic ld tests lwax, lwaux commit | commitdiff | tree
2020-08-23 Michael NolanAdd copyright to files I primarily authored in simulator/ commit | commitdiff | tree
2020-08-23 Michael NolanAdd copyright to files in fu/ that I was the primary... commit | commitdiff | tree
2020-08-23 Michael NolanAdd copyright statement to power_decoder.py commit | commitdiff | tree
2020-08-23 Luke Kenneth... bring "core stopped" signal out through DMI interface commit | commitdiff | tree
2020-08-23 Luke Kenneth... add in DMI "stat" loop which monitors core "stopping" commit | commitdiff | tree
2020-08-23 Cesar StraussAllow an empty style, and passing default styles as... commit | commitdiff | tree
2020-08-23 Cesar StraussAdd comment node type commit | commitdiff | tree
2020-08-23 Cesar StraussAdd base and display styles commit | commitdiff | tree
2020-08-23 Cesar StraussApply style from node own name commit | commitdiff | tree
2020-08-23 Cesar StraussAdd color style commit | commitdiff | tree
2020-08-23 Cesar StraussCollect styles from the tuple commit | commitdiff | tree
2020-08-23 Cesar StraussPropagate the root style to all signals commit | commitdiff | tree
2020-08-23 Luke Kenneth... comment why litex sim mem map is altered commit | commitdiff | tree
2020-08-23 Luke Kenneth... multiply does not have invert_in, zero_a or invert_out commit | commitdiff | tree
2020-08-22 Luke Kenneth... rename invert_a to invert_in because logical inverts RB commit | commitdiff | tree
2020-08-22 Luke Kenneth... update submodule commit | commitdiff | tree
2020-08-22 Luke Kenneth... load bios not 1.bin unit test commit | commitdiff | tree
2020-08-22 Luke Kenneth... add extra div regression tests commit | commitdiff | tree
2020-08-22 Cesar StraussMove comments to the docstring commit | commitdiff | tree
2020-08-22 Cesar StraussWalk the DOM and emit the trace names commit | commitdiff | tree
2020-08-22 Luke Kenneth... add eqv to logical unit test commit | commitdiff | tree
2020-08-22 Luke Kenneth... add nor and nand to unit test commit | commitdiff | tree
2020-08-22 Luke Kenneth... moved to div pipe temporarily in compunits commit | commitdiff | tree
2020-08-22 Luke Kenneth... bug in andc and orc, complement was taking place on... commit | commitdiff | tree
2020-08-22 Luke Kenneth... extend addis test commit | commitdiff | tree
2020-08-22 Luke Kenneth... add andc and orc tests, failing because RB needs invers... commit | commitdiff | tree
2020-08-22 Luke Kenneth... modsd bug, https://bugs.libre-soc.org/show_bug.cgi... commit | commitdiff | tree
2020-08-22 Cesar StraussFirst draft of a mini-language to describe GTKWave... commit | commitdiff | tree
2020-08-22 Luke Kenneth... submodule update commit | commitdiff | tree
2020-08-22 Luke Kenneth... add regression test for nonzero addis commit | commitdiff | tree
2020-08-22 Luke Kenneth... add means to run microwatt test binaries commit | commitdiff | tree
2020-08-22 Luke Kenneth... r0 zero tests on addis, fails commit | commitdiff | tree
2020-08-22 Luke Kenneth... investigating litex sdrinit function commit | commitdiff | tree
2020-08-22 Luke Kenneth... add pseudo-op conversion commit | commitdiff | tree
2020-08-22 Luke Kenneth... add start of litex bios counter loop commit | commitdiff | tree
2020-08-21 Luke Kenneth... remove extraneous comments commit | commitdiff | tree
2020-08-21 Luke Kenneth... testing 64-bit wishbone bus after 32-bit *still* fails... commit | commitdiff | tree
2020-08-21 Tobias Platentypo fix in test_l0_cache_buffer2.py commit | commitdiff | tree
2020-08-21 Cole Poirierdcache.py fix asserts, use backslash and two strings... commit | commitdiff | tree
2020-08-21 Cole Poirierdcache.py replace functions that return signals with... commit | commitdiff | tree
2020-08-21 Cole Poirierwb_types fix typo commit | commitdiff | tree
2020-08-21 Tobias Platenconnect TestCachedMemoryPortInterface to LDSTSplitter commit | commitdiff | tree
2020-08-21 Luke Kenneth... get litex sim enabled with 32-bit wishbone bus commit | commitdiff | tree
2020-08-21 Luke Kenneth... ld/st bus reduction test operational commit | commitdiff | tree
2020-08-21 Luke Kenneth... first test of down-converted load/store from 64 to... commit | commitdiff | tree
2020-08-21 Luke Kenneth... first test of down-converted load/store from 64 to... commit | commitdiff | tree
2020-08-21 Luke Kenneth... add in WishboneDownConvert into LoadStoreUnitInterface commit | commitdiff | tree
2020-08-21 Luke Kenneth... comment formatting commit | commitdiff | tree
2020-08-21 Luke Kenneth... remove default values commit | commitdiff | tree
2020-08-21 Luke Kenneth... just range(the_constant) commit | commitdiff | tree
2020-08-21 Samuel A. Falvo IIMUL pipeline WIP: mullw and mullwu covered. commit | commitdiff | tree
2020-08-21 Samuel A. Falvo IIMUL pipeline: account for overflow flags. WIP commit | commitdiff | tree
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc commit | commitdiff | tree
2020-08-21 Cole Poirierdcache.py commit today and yesterday's progress (sorry... commit | commitdiff | tree
2020-08-21 Samuel A. Falvo IIMUL pipeline proofs: mulli / mullw WIP. commit | commitdiff | tree
2020-08-20 Samuel A. Falvo IIMUL pipeline proof: muldw(u) commit | commitdiff | tree
2020-08-20 Samuel A. Falvo IIMUL pipeline proof: signed mulhw commit | commitdiff | tree
2020-08-20 Tobias Platenstart wiring TestCachedMemoryPortInterface commit | commitdiff | tree
2020-08-20 Tobias Platentestcase refactoring commit | commitdiff | tree
2020-08-20 Tobias Platenadd new class TestCachedMemoryPortInterface commit | commitdiff | tree
2020-08-20 Luke Kenneth... bugfix wishbone downconvert using wb sram 64-to-32... commit | commitdiff | tree
2020-08-20 Luke Kenneth... add a wishbone upconverter commit | commitdiff | tree
2020-08-19 Luke Kenneth... rename and document fields in shift_rot proof commit | commitdiff | tree
2020-08-19 Luke Kenneth... comments in dcache commit | commitdiff | tree
2020-08-19 Luke Kenneth... more subtle interactions between wishbone bus when... commit | commitdiff | tree
2020-08-19 Luke Kenneth... bit of a reorg of mul proof, tracking down missing commit | commitdiff | tree
2020-08-19 Luke Kenneth... move long mul tests to separate unit test commit | commitdiff | tree
2020-08-19 Luke Kenneth... use "Mask" class which is more gate-efficient than... commit | commitdiff | tree
2020-08-19 Samuel A. Falvo IIWIP: OP_MUL proofs started. commit | commitdiff | tree
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