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riscv-tests.git
2018-11-02
Luke Kenneth...
additional sv flw elwidth tests
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2018-11-02
Luke Kenneth...
still experimenting with sv flw elwidth unit test
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2018-11-02
Luke Kenneth...
add 32-bit FLW unit tests
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2018-11-01
Luke Kenneth...
add alignment on testdata
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2018-11-01
Luke Kenneth...
add extra fp16 fld tests
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2018-11-01
Luke Kenneth...
add 32-16 fld unit test
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2018-11-01
Luke Kenneth...
working on sv fld elwidth variant
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2018-10-31
Luke Kenneth...
add sv fld elwidth test
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2018-10-31
Luke Kenneth...
add unit test for fp16 2-packed
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2018-10-31
Luke Kenneth...
working towards sv fp elwidth
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2018-10-31
Luke Kenneth...
test of fp16 elwidth
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2018-10-30
Luke Kenneth...
add fp add elwidth single-precision test
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2018-10-30
Luke Kenneth...
add comment string
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2018-10-30
Luke Kenneth...
add extra unit tests
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2018-10-30
Luke Kenneth...
add VL arg to macro
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2018-10-30
Luke Kenneth...
add isvec args to test elwidth macros
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2018-10-29
Luke Kenneth...
add sv store elementwidth test
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2018-10-29
Luke Kenneth...
add extra ld elwidth tests, add #defines for elwidths
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2018-10-29
Luke Kenneth...
add extra tests, change data (unsigned in places)
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2018-10-29
Luke Kenneth...
add sv_ld_elwidth test
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2018-10-29
Luke Kenneth...
add in TODO list
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2018-10-26
Luke Kenneth...
extend addw bitwidth test to 3 registers
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2018-10-26
Luke Kenneth...
put in stuff that should not be overwritten
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2018-10-26
Luke Kenneth...
correct addw elwidth test
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2018-10-26
Luke Kenneth...
sv addw variable elwidth unit test
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2018-10-26
Luke Kenneth...
sort out registers and add extra unit tests for add...
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2018-10-26
Luke Kenneth...
add sv_add_elwidth unit test
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2018-10-16
Luke Kenneth...
modified VL and MVL CSRs to range from 1-XLEN rather...
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2018-10-09
Luke Kenneth...
add sv vectorised predicated beq test
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2018-10-09
Luke Kenneth...
alter unit tests to match change in CSR table format
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2018-10-07
Luke Kenneth...
add cleanup and comments to sv lwsp pred test
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2018-10-07
Luke Kenneth...
add predicated version of c.lwsp sv unit test
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2018-10-07
Luke Kenneth...
add 3rd register to c.swsp
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2018-10-07
Luke Kenneth...
add 3 registers to sv c.lwsp
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2018-10-07
Luke Kenneth...
add s.swsp sv test
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2018-10-06
Luke Kenneth...
add sv c_lwsp unit test
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2018-10-05
Luke Kenneth...
whoops overwrote x2
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2018-10-04
Luke Kenneth...
add twin-predicated sv c_mv unit test (no zeroing)
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2018-10-04
Luke Kenneth...
add sv c.mv twin-predication unit test
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2018-10-02
Luke Kenneth...
actually sv vector-vector add worked fine
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2018-10-02
Luke Kenneth...
add rv64ud sv fadd test, shows flaw in loop for 3-arg...
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2018-10-01
Luke Kenneth...
add vector-vector sv add
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2018-10-01
Luke Kenneth...
add sv addi predicated unit test, including inversion...
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2018-10-01
Luke Kenneth...
add extra sv test comments
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2018-10-01
Luke Kenneth...
update sv test comments
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2018-10-01
Luke Kenneth...
add sv scalar src test which highlighted flaw in spike-sv
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2018-10-01
Luke Kenneth...
add redirection sv unit test
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2018-10-01
Luke Kenneth...
augment sv_addi test using macros
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2018-10-01
Luke Kenneth...
add first unit test for simple-v
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2018-09-24
Andrew Waterman
bump env
master
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2018-09-13
Tim Newsome
Assert if HiFive1 program is too large.
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2018-09-13
Tim Newsome
Put debug test stack in data instead of text
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2018-09-08
Andrew Waterman
Merge branch 'tommythorn-master'
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2018-09-08
Tommy Thorn
RV64 s{ll,ra,rl}w tests with non-canonical values
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2018-09-07
Andrew Waterman
Revert "breakpoint.S: Don't assume trigger is hardwired...
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2018-09-06
Tommy Thorn
breakpoint.S: Don't assume trigger is hardwired to...
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2018-09-03
Tim Newsome
Merge pull request #156 from riscv/PrivChange
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2018-08-31
Tim Newsome
Fix CustomRegisterTest.
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2018-08-29
Tim Newsome
Add test case for `riscv expose_custom`.
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2018-08-28
Tim Newsome
Reset address translation/perms before PrivChange
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2018-08-28
Tim Newsome
Neuter TriggerStoreAddressInstant
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2018-08-27
Tim Newsome
Make pylint happy.
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2018-08-25
Andrew Waterman
Temporarily disabling PrivChange test
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2018-08-24
Tim Newsome
Make pylint happy with change d1d2d953b5016b465.
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2018-08-24
Tim Newsome
Get all of the log into the final log file
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2018-08-23
Tim Newsome
Merge pull request #153 from dmitryryzhov/rtos-switch...
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2018-08-22
Tim Newsome
Merge branch 'master' of https://github.com/riscv/riscv...
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2018-08-22
Tim Newsome
Disable MulticoreRunHaltStepiTest
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2018-08-22
Dmitry Ryzhov
Add debug test, which checks that openocd correctly...
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2018-08-21
Srivatsa Yogendra
Changing the register mstatus is read into (#152)
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2018-08-21
Andrew Waterman
Revert "Fix to solve the failing tests shamt, csr and...
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2018-08-18
Srivatsa Yogendra
Fix to solve the failing tests shamt, csr and scall...
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2018-08-17
Srivatsa Yogendra
making mtvec_handler global (#150)
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2018-08-13
Tim Newsome
Add jump/hbreak test.
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2018-07-09
Andrew Waterman
Check that SC yields the load reservation
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2018-07-03
Tim Newsome
rwatch/watch on explicit address
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2018-06-18
Tim Newsome
Add reproduce line to the end of debug test logs
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2018-05-21
Tim Newsome
Merge pull request #141 from riscv/mrhstest
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2018-05-19
Tim Newsome
Fix MulticoreRunHaltStepiTest
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2018-05-15
Megan Wachs
Merge pull request #139 from riscv/debug-tests-more...
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2018-05-14
Megan Wachs
Merge remote-tracking branch 'origin/downloadtest'...
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2018-05-14
Tim Newsome
Make DownloadTest properly park other harts.
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2018-05-14
Megan Wachs
debug: remove some unintentionally added newlines
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2018-05-14
Megan Wachs
debug: Fixing the non-RTOS behavior for DownloadTest
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2018-05-11
Megan Wachs
debug: mark more tests as single-hart tests
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2018-05-11
Megan Wachs
debug: output some more useful info into the post-morte...
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2018-05-01
Christopher...
[rv64ua/lrsc] Initialize memory read out. (#135)
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2018-04-30
Tim Newsome
Fix formatting to make pylint happy.
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2018-04-29
Megan Wachs
Merge pull request #132 from riscv/debug-clear-satp
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2018-04-27
Megan Wachs
debug: need to clear satp before changing priv
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2018-04-27
Megan Wachs
Merge pull request #125 from riscv/debug-delete-sim
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2018-04-27
Megan Wachs
Merge pull request #130 from riscv/trap_entry_align-1
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2018-04-27
Megan Wachs
debug: add missing align directive on trap_entry
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2018-04-24
Tim Newsome
Fix race when making logs directory
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2018-04-19
Megan Wachs
Delete E300Sim.py
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2018-04-16
Tim Newsome
Merge pull request #123 from riscv/gdb_timeout
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2018-04-09
Tim Newsome
Compute gdb command timeout based on ops estimate
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2018-04-09
Andrei Tatarnikov
Fix #120: Instructions 'sll' are replaced with 'slli...
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2018-04-02
Tim Newsome
Use `gdb_report_register_access_error enable`
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2018-03-27
Tim Newsome
Test debug authentication.
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