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soc.git
2020-12-09 Luke Kenneth... update submodules commit | commitdiff | tree
2020-12-07 Cesar StraussDisplay the instruction type as a vector on cxxsim commit | commitdiff | tree
2020-12-06 Luke Kenneth... attempt to split into two separate GPIO banks due to... commit | commitdiff | tree
2020-12-06 Cesar StraussWhitespace commit | commitdiff | tree
2020-12-06 Cesar StraussUpdate GTKWave documents to work with latest cxxsim commit | commitdiff | tree
2020-12-05 Cesar StraussWrite a GTKWave document to investigate why the proof... commit | commitdiff | tree
2020-12-05 Cesar StraussUse the DummyALU regspec and its corresponding OpSubset commit | commitdiff | tree
2020-12-03 Luke Kenneth... put ls180 litex bus width back to 32 bit temporarily commit | commitdiff | tree
2020-12-03 Luke Kenneth... argh issue with yosys ABC commit | commitdiff | tree
2020-12-03 Luke Kenneth... add 3 more 4k SRAMs, change WB bus width to 64 in ls180... commit | commitdiff | tree
2020-11-28 Cesar StraussFix signal names: go/rel -> go_i/rel_o commit | commitdiff | tree
2020-11-24 Cesar StraussFix some typos and whitespace commit | commitdiff | tree
2020-11-24 Cesar StraussPort the DummyALU test case to the new parallel issuer commit | commitdiff | tree
2020-11-23 Cesar StraussResults are now a list, so "expected" should follow... commit | commitdiff | tree
2020-11-23 Cesar StraussParameterize the issuer on the number of operands and... commit | commitdiff | tree
2020-11-22 Cesar StraussRefactor the ALU operation issuer into a class commit | commitdiff | tree
2020-11-22 Cesar StraussPort the ALU test case to the new parallel test style commit | commitdiff | tree
2020-11-22 Cesar StraussAdd a GTKWave document to the ALU test case commit | commitdiff | tree
2020-11-22 Luke Kenneth... simplify litex-core wishbone interfaces commit | commitdiff | tree
2020-11-19 Cesar StraussSeparate input and output ports by color commit | commitdiff | tree
2020-11-19 Cesar StraussExplain the test cases commit | commitdiff | tree
2020-11-18 Cesar StraussSeparate individual traces for each rel_o/go_i port commit | commitdiff | tree
2020-11-17 Tobias Platentestcase for dcbz commit | commitdiff | tree
2020-11-16 Cesar StraussAdd a transaction counter to producers and consumers commit | commitdiff | tree
2020-11-16 Tobias Platenadd class LoadStore1(PortInterfaceBase) commit | commitdiff | tree
2020-11-15 Cesar StraussImplement ResultConsumer and port the Shifter unit... commit | commitdiff | tree
2020-11-14 Cesar StraussMove the DUT driver to within the test case process commit | commitdiff | tree
2020-11-14 Cesar StraussFix and enable the regspec test for the Shifter commit | commitdiff | tree
2020-11-14 Luke Kenneth... sigh, direction wrong in IOtypes litex core commit | commitdiff | tree
2020-11-13 Luke Kenneth... reduce number of nc in ls180 to 24 commit | commitdiff | tree
2020-11-13 Luke Kenneth... reduce clkcsel ls180 width (2 pins), rename pll_18... commit | commitdiff | tree
2020-11-13 Luke Kenneth... rename and add pll lock signal to ls180 commit | commitdiff | tree
2020-11-13 Luke Kenneth... rename ls180 litex pll_48 output to pll_18 commit | commitdiff | tree
2020-11-13 Luke Kenneth... add enable/disable arguments (not ideal but it works... commit | commitdiff | tree
2020-11-13 Luke Kenneth... remove io_in/out now it is not needed for niolib commit | commitdiff | tree
2020-11-11 Tobias Platendcbz and tlbie first test, still incomplete commit | commitdiff | tree
2020-11-11 Tobias Platenfu/mmu/test/test_pipe_caller.py test case for mfspr commit | commitdiff | tree
2020-11-10 Luke Kenneth... add build commands to Makefile for versa ecp5 commit | commitdiff | tree
2020-11-10 Luke Kenneth... submodule update commit | commitdiff | tree
2020-11-10 Luke Kenneth... remove ClockSelect module, use DummyPLL commit | commitdiff | tree
2020-11-10 Luke Kenneth... add separate DummyPLL module, according to API discussed at commit | commitdiff | tree
2020-11-08 Tobias Platenmmu fsm testcase: add check_fsm_outputs based on functi... commit | commitdiff | tree
2020-11-08 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org... commit | commitdiff | tree
2020-11-08 Tobias Platenmmu/fsm: test case for mtspr commit | commitdiff | tree
2020-11-07 Luke Kenneth... update submodule commit | commitdiff | tree
2020-11-07 Tobias Platenfixed a bug in src/soc/fu/mmu/fsm.py commit | commitdiff | tree
2020-11-06 Luke Kenneth... sigh sorting out litex pin-connections to sdram commit | commitdiff | tree
2020-11-04 Luke Kenneth... move back to 3.3v on X3 VERSA ECP5 connector commit | commitdiff | tree
2020-11-04 Tobias PlatenMMU: begin test case for 'dcbz' commit | commitdiff | tree
2020-11-03 Tobias Platenfix broken unittest after installing power-instruction... commit | commitdiff | tree
2020-11-03 Luke Kenneth... swap jtag pinorder to match ulx3s commit | commitdiff | tree
2020-11-03 Luke Kenneth... change LVCMOS level on versa ecp5 jtag to 2.5v commit | commitdiff | tree
2020-11-01 Cesar StraussAdd a check for liveness. commit | commitdiff | tree
2020-10-31 Cole Poirierversa_ecp5.py add 4 arbitrarily assigned gpio pins... commit | commitdiff | tree
2020-10-31 Cesar StraussCheck that the read and write counters differ at most... commit | commitdiff | tree
2020-10-31 Cesar StraussRemove stray comment commit | commitdiff | tree
2020-10-30 Luke Kenneth... add JTAG extension to versa_ecp5 then we can use it commit | commitdiff | tree
2020-10-28 Cesar StraussImplement an operand producer that talks the rel_o... commit | commitdiff | tree
2020-10-24 Luke Kenneth... submodule update commit | commitdiff | tree
2020-10-24 Cesar StraussCreate a GTKWave document for the test ALU unit tests commit | commitdiff | tree
2020-10-22 Luke Kenneth... add query about cross-domain on the JTAG enable of WB commit | commitdiff | tree
2020-10-22 Luke Kenneth... add detection and disable of Instruction Wishbone based... commit | commitdiff | tree
2020-10-22 Luke Kenneth... add detection and disable of LoadStore Wishbone based... commit | commitdiff | tree
2020-10-22 Luke Kenneth... add JTAG enable/disable of wishbone to TestIssuer commit | commitdiff | tree
2020-10-22 Luke Kenneth... add means to JTAG interface to enable/disable "stuff... commit | commitdiff | tree
2020-10-21 Cole Poirierversa_ecp5 adds ability to build and load for ulx3s85f... commit | commitdiff | tree
2020-10-21 Luke Kenneth... fix up asserts (check correct pads/cores) commit | commitdiff | tree
2020-10-20 Tobias Platens/alu/fsm/g commit | commitdiff | tree
2020-10-20 Tobias Platentest case for FSMMMUStage commit | commitdiff | tree
2020-10-18 Cole Poirieruse random.seed to generate repro cases of the two... commit | commitdiff | tree
2020-10-16 Luke Kenneth... experiment swapping dummy trap stage over to input commit | commitdiff | tree
2020-10-16 Luke Kenneth... re-enable tests commit | commitdiff | tree
2020-10-16 Luke Kenneth... manually run coresync clock for test issuer commit | commitdiff | tree
2020-10-16 Luke Kenneth... set defaults in pspec commit | commitdiff | tree
2020-10-16 Luke Kenneth... update submodule commit | commitdiff | tree
2020-10-16 Luke Kenneth... add extra (test dummy stage in trap to see if combinato... commit | commitdiff | tree
2020-10-16 Luke Kenneth... add LGPLv3+ notice and add copyright holders commit | commitdiff | tree
2020-10-15 Luke Kenneth... add commented-out connection to JTAG in ECP5 litex commit | commitdiff | tree
2020-10-15 Luke Kenneth... wrong pspec variable in selecting pll clock commit | commitdiff | tree
2020-10-15 Luke Kenneth... sorting out missing clock somewhere commit | commitdiff | tree
2020-10-15 Luke Kenneth... use "enable" and set default actions in getopt commit | commitdiff | tree
2020-10-15 Luke Kenneth... add extra variant to litex core commit | commitdiff | tree
2020-10-15 Luke Kenneth... syntax error commit | commitdiff | tree
2020-10-15 Luke Kenneth... disable gpio in litex core commit | commitdiff | tree
2020-10-15 Luke Kenneth... enable/disable litex irqs based on variant name commit | commitdiff | tree
2020-10-14 Cole PoirierMakefile develop, when running setup.py develop specify... commit | commitdiff | tree
2020-10-14 Cole Poirierissuer_verilog.py update to use commandline args using... commit | commitdiff | tree
2020-10-13 Cole Poiriermove pia from install_requires to test_requires commit | commitdiff | tree
2020-10-12 Cole Poirierlitex/florent/versa_ecp5.py add arg --fpga [versa_ecp5... commit | commitdiff | tree
2020-10-12 Cole Poirierfix ModuleNotFound/Import errors found when running... commit | commitdiff | tree
2020-10-12 Tobias Platenupdate gitlab ci commit | commitdiff | tree
2020-10-12 Cole Poirieradd tested working fpga compile/build/load file for... commit | commitdiff | tree
2020-10-11 Luke Kenneth... add way to bypass PLL for ECP5 and sim commit | commitdiff | tree
2020-10-11 Luke Kenneth... comment out XICS/GPIO interrupt test, causes ECP5 litex... commit | commitdiff | tree
2020-10-11 Luke Kenneth... record commands for building ECP5 commit | commitdiff | tree
2020-10-11 Luke Kenneth... litex sim.py operational commit | commitdiff | tree
2020-10-10 Cole Poirierflorent/versa_ecp5.py remove uneccessary imports, speci... commit | commitdiff | tree
2020-10-10 Luke Kenneth... add debug start/stop to firmware_upload script commit | commitdiff | tree
2020-10-10 Luke Kenneth... add DMI status / reset to firmware upload script commit | commitdiff | tree
2020-10-10 Luke Kenneth... add first version of firmware uploader commit | commitdiff | tree
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