2020-05-30 |
Luke Kenneth... | mess - but a functional mess. ALU-MultiCompUnit semi... |
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2020-05-30 |
Luke Kenneth... | grab other results from ALU pipeline in compunit test |
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2020-05-30 |
Luke Kenneth... | order of XER so/ca wrong way round from regspec |
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2020-05-30 |
Luke Kenneth... | still experimenting with ALU-CompUnit interaction |
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2020-05-29 |
Luke Kenneth... | interesting. use of Settle() works, showing that Regfi... |
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2020-05-29 |
Luke Kenneth... | module comments for popcount |
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2020-05-29 |
Luke Kenneth... | comments on popcount |
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2020-05-29 |
Luke Kenneth... | trigger ALU ready when operands ready |
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2020-05-29 |
Tobias Platen | fixes for DataMerger |
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2020-05-29 |
Luke Kenneth... | trigger read ALU ready/valid from latch as well |
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2020-05-29 |
Luke Kenneth... | use a latch to communicate read/valid output from ALU |
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2020-05-29 |
Tobias Platen | DataMerger: rename addr_match_i to addr_array_i |
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2020-05-29 |
Tobias Platen | fixed 'return m is missing' |
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2020-05-29 |
Tobias Platen | whitespace fixes |
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2020-05-29 |
Luke Kenneth... | latch all output on ALU output valid |
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2020-05-29 |
Luke Kenneth... | create read-done pulse |
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2020-05-29 |
Luke Kenneth... | write-release moves out of "ALU valid" due to using... |
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2020-05-29 |
Luke Kenneth... | signal start of request from when ALU triggers result... |
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2020-05-29 |
Luke Kenneth... | create rising pulse from ALU valid |
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2020-05-29 |
Luke Kenneth... | names of attributes needs to be dest_o not dest_i |
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2020-05-29 |
Luke Kenneth... | rename output signals in Test ALU |
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2020-05-29 |
Cesar Strauss | Allow immediate assertion of go in the same cycle as rel |
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2020-05-29 |
Cesar Strauss | Correct typo |
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2020-05-29 |
Cesar Strauss | Send a one-clock "go" pulse after a configurable number... |
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2020-05-28 |
Luke Kenneth... | messing about with proof_regfile.py |
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2020-05-28 |
Luke Kenneth... | move simple_popcount out of class (does not use any... |
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2020-05-28 |
colepoirier | Added Initial() synchronous check with draft truth |
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2020-05-28 |
Luke Kenneth... | extra check on rd.req in test_alu_compunit |
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2020-05-28 |
Tobias Platen | indention |
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2020-05-28 |
Michael Nolan | Add proof for OP_SETB |
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2020-05-28 |
Michael Nolan | Update to latest wiki version |
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2020-05-28 |
Michael Nolan | Add OP_SETB |
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2020-05-28 |
Michael Nolan | Fix test_isel to properly examine registers |
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2020-05-28 |
Tobias Platen | unittest for DataMerger |
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2020-05-28 |
Tobias Platen | more fixes for DataMerger |
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2020-05-28 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-05-28 |
Tobias Platen | fixes for l0_cache.py |
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2020-05-28 |
Luke Kenneth... | debug-print rd/wr rel in test_alu_compunit |
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2020-05-28 |
Luke Kenneth... | add quick test of 3-operand DummyALU in MultiCompALU |
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2020-05-28 |
Luke Kenneth... | add 3rd parameter to DummyALU |
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2020-05-28 |
Luke Kenneth... | debugging test_alu_compunit.py |
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2020-05-28 |
Luke Kenneth... | start on a compunit ALU test |
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2020-05-28 |
Luke Kenneth... | update comment |
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2020-05-28 |
Luke Kenneth... | remove trick of not setting SO |
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2020-05-28 |
Cesar Strauss | Check that rd rises after issue_i, unless it's immediate |
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2020-05-28 |
Luke Kenneth... | hmm.... |
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2020-05-28 |
colepoirier | Add sync Assert for _wrports 'wen' signal in proof_regf... |
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2020-05-28 |
Cesar Strauss | Store and present parameters together with issue_i |
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2020-05-27 |
Luke Kenneth... | do not use range(0, x) - just range(x) |
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2020-05-27 |
Luke Kenneth... | remove write-block on register zero |
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2020-05-27 |
Luke Kenneth... | code-morph, add TODO on OP_RFID, OP_SC, OP_ADDPCIS |
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2020-05-27 |
colepoirier | Derive proof_regfile Driver from regfile.Register(... |
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2020-05-27 |
colepoirier | Fix indentation of regfile/formal/proof_regfile.py |
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2020-05-27 |
colepoirier | First commit of proof of regfile, not working yet |
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2020-05-27 |
Luke Kenneth... | add LD/ST pipe_data |
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2020-05-27 |
Luke Kenneth... | LogicalOutputData does not need XER.so |
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2020-05-27 |
Luke Kenneth... | comments |
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2020-05-27 |
Luke Kenneth... | remove XER.ca from logical Input Data - not needed |
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2020-05-27 |
Luke Kenneth... | cleanup logical main proof |
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2020-05-27 |
Luke Kenneth... | check cr0, ov and ca ok signals in ALU main_stage proof |
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2020-05-27 |
Luke Kenneth... | add carry-out, overflow and cr0 ok setting in ALU main_... |
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2020-05-27 |
Luke Kenneth... | add SRR0 to TrapInputData |
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2020-05-27 |
Luke Kenneth... | add links to bugreports into ALu formal proof as well |
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2020-05-27 |
Luke Kenneth... | add links to bugreports into alu output stage proof |
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2020-05-27 |
Luke Kenneth... | check reg output Data.ok in shift_rot formal proof |
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2020-05-27 |
Luke Kenneth... | rename CROutputData.cr_o to just CROutputData.cr |
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2020-05-27 |
Luke Kenneth... | test Data.ok for cr output and full cr output |
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2020-05-27 |
Luke Kenneth... | assign and test on Data, TODO add Data.ok checking... |
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2020-05-27 |
Michael Nolan | Fix bug in alu main stage proof |
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2020-05-27 |
Cesar Strauss | Move test case parameters to an "operation" member... |
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2020-05-27 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2020-05-27 |
Tobias Platen | elaborate function for DataMerger |
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2020-05-27 |
Cesar Strauss | Remove the monitor process |
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2020-05-27 |
Luke Kenneth... | make power function unit enum bitmasked |
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2020-05-27 |
Luke Kenneth... | add extra INT regs port for now, add Fast Regfile |
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2020-05-27 |
Luke Kenneth... | added XER and CR regfiles, using new VirtualRegPort |
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2020-05-26 |
Luke Kenneth... | check assertions |
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2020-05-26 |
Luke Kenneth... | make read/write regs properly internal |
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2020-05-26 |
Luke Kenneth... | add VirtualRegPort test, seems to demonstrate it working |
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2020-05-26 |
Luke Kenneth... | remove sync (not needed) |
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2020-05-26 |
Luke Kenneth... | get score6600_multi.py working again |
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2020-05-26 |
Luke Kenneth... | redo focus of virtual reg port to do only full datawidt... |
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2020-05-26 |
Michael Nolan | Add extras from bottom of the file |
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2020-05-26 |
Michael Nolan | Rewrite proof to be more in line with what appears... |
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2020-05-26 |
Luke Kenneth... | sort-of (maybe) implemented a virtual port on top of... |
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2020-05-26 |
Luke Kenneth... | try new variant of VirtualRegFile |
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2020-05-26 |
Luke Kenneth... | use nmutil treereduce |
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2020-05-26 |
Luke Kenneth... | continue virtual regfile port |
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2020-05-26 |
Luke Kenneth... | whitespace, add commentary |
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2020-05-26 |
colepoirier | First attempt at implementing block access rd and wr... |
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2020-05-25 |
Cesar Strauss | Check that busy_o doesn't rise on its own |
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2020-05-25 |
Cesar Strauss | Implement the issue_i/busy_o protocol check. |
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2020-05-25 |
Cesar Strauss | Move process list to CompUnitParallelTest |
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2020-05-25 |
Michael Nolan | Correct polarity of shadow signal |
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2020-05-25 |
Luke Kenneth... | document shadown inversion |
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2020-05-25 |
Michael Nolan | Add link to compunit wiki page |
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2020-05-25 |
Michael Nolan | Correct property numbers, add assertions about busy |
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2020-05-25 |
Luke Kenneth... | update comments on compalu_multi.py |
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2020-05-25 |
Michael Nolan | Add assertions about go_wr and wr_rel |
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2020-05-25 |
Michael Nolan | Minor cleanup of comments |
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next |