soc.git
2020-05-30 Luke Kenneth... mess - but a functional mess. ALU-MultiCompUnit semi...
2020-05-30 Luke Kenneth... grab other results from ALU pipeline in compunit test
2020-05-30 Luke Kenneth... order of XER so/ca wrong way round from regspec
2020-05-30 Luke Kenneth... still experimenting with ALU-CompUnit interaction
2020-05-29 Luke Kenneth... interesting. use of Settle() works, showing that Regfi...
2020-05-29 Luke Kenneth... module comments for popcount
2020-05-29 Luke Kenneth... comments on popcount
2020-05-29 Luke Kenneth... trigger ALU ready when operands ready
2020-05-29 Tobias Platenfixes for DataMerger
2020-05-29 Luke Kenneth... trigger read ALU ready/valid from latch as well
2020-05-29 Luke Kenneth... use a latch to communicate read/valid output from ALU
2020-05-29 Tobias PlatenDataMerger: rename addr_match_i to addr_array_i
2020-05-29 Tobias Platenfixed 'return m is missing'
2020-05-29 Tobias Platenwhitespace fixes
2020-05-29 Luke Kenneth... latch all output on ALU output valid
2020-05-29 Luke Kenneth... create read-done pulse
2020-05-29 Luke Kenneth... write-release moves out of "ALU valid" due to using...
2020-05-29 Luke Kenneth... signal start of request from when ALU triggers result...
2020-05-29 Luke Kenneth... create rising pulse from ALU valid
2020-05-29 Luke Kenneth... names of attributes needs to be dest_o not dest_i
2020-05-29 Luke Kenneth... rename output signals in Test ALU
2020-05-29 Cesar StraussAllow immediate assertion of go in the same cycle as rel
2020-05-29 Cesar StraussCorrect typo
2020-05-29 Cesar StraussSend a one-clock "go" pulse after a configurable number...
2020-05-28 Luke Kenneth... messing about with proof_regfile.py
2020-05-28 Luke Kenneth... move simple_popcount out of class (does not use any...
2020-05-28 colepoirierAdded Initial() synchronous check with draft truth
2020-05-28 Luke Kenneth... extra check on rd.req in test_alu_compunit
2020-05-28 Tobias Platenindention
2020-05-28 Michael NolanAdd proof for OP_SETB
2020-05-28 Michael NolanUpdate to latest wiki version
2020-05-28 Michael NolanAdd OP_SETB
2020-05-28 Michael NolanFix test_isel to properly examine registers
2020-05-28 Tobias Platenunittest for DataMerger
2020-05-28 Tobias Platenmore fixes for DataMerger
2020-05-28 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-28 Tobias Platenfixes for l0_cache.py
2020-05-28 Luke Kenneth... debug-print rd/wr rel in test_alu_compunit
2020-05-28 Luke Kenneth... add quick test of 3-operand DummyALU in MultiCompALU
2020-05-28 Luke Kenneth... add 3rd parameter to DummyALU
2020-05-28 Luke Kenneth... debugging test_alu_compunit.py
2020-05-28 Luke Kenneth... start on a compunit ALU test
2020-05-28 Luke Kenneth... update comment
2020-05-28 Luke Kenneth... remove trick of not setting SO
2020-05-28 Cesar StraussCheck that rd rises after issue_i, unless it's immediate
2020-05-28 Luke Kenneth... hmm....
2020-05-28 colepoirierAdd sync Assert for _wrports 'wen' signal in proof_regf...
2020-05-28 Cesar StraussStore and present parameters together with issue_i
2020-05-27 Luke Kenneth... do not use range(0, x) - just range(x)
2020-05-27 Luke Kenneth... remove write-block on register zero
2020-05-27 Luke Kenneth... code-morph, add TODO on OP_RFID, OP_SC, OP_ADDPCIS
2020-05-27 colepoirierDerive proof_regfile Driver from regfile.Register(...
2020-05-27 colepoirierFix indentation of regfile/formal/proof_regfile.py
2020-05-27 colepoirierFirst commit of proof of regfile, not working yet
2020-05-27 Luke Kenneth... add LD/ST pipe_data
2020-05-27 Luke Kenneth... LogicalOutputData does not need XER.so
2020-05-27 Luke Kenneth... comments
2020-05-27 Luke Kenneth... remove XER.ca from logical Input Data - not needed
2020-05-27 Luke Kenneth... cleanup logical main proof
2020-05-27 Luke Kenneth... check cr0, ov and ca ok signals in ALU main_stage proof
2020-05-27 Luke Kenneth... add carry-out, overflow and cr0 ok setting in ALU main_...
2020-05-27 Luke Kenneth... add SRR0 to TrapInputData
2020-05-27 Luke Kenneth... add links to bugreports into ALu formal proof as well
2020-05-27 Luke Kenneth... add links to bugreports into alu output stage proof
2020-05-27 Luke Kenneth... check reg output Data.ok in shift_rot formal proof
2020-05-27 Luke Kenneth... rename CROutputData.cr_o to just CROutputData.cr
2020-05-27 Luke Kenneth... test Data.ok for cr output and full cr output
2020-05-27 Luke Kenneth... assign and test on Data, TODO add Data.ok checking...
2020-05-27 Michael NolanFix bug in alu main stage proof
2020-05-27 Cesar StraussMove test case parameters to an "operation" member...
2020-05-27 Tobias PlatenMerge branch 'master' of ssh://git.libre-riscv.org...
2020-05-27 Tobias Platenelaborate function for DataMerger
2020-05-27 Cesar StraussRemove the monitor process
2020-05-27 Luke Kenneth... make power function unit enum bitmasked
2020-05-27 Luke Kenneth... add extra INT regs port for now, add Fast Regfile
2020-05-27 Luke Kenneth... added XER and CR regfiles, using new VirtualRegPort
2020-05-26 Luke Kenneth... check assertions
2020-05-26 Luke Kenneth... make read/write regs properly internal
2020-05-26 Luke Kenneth... add VirtualRegPort test, seems to demonstrate it working
2020-05-26 Luke Kenneth... remove sync (not needed)
2020-05-26 Luke Kenneth... get score6600_multi.py working again
2020-05-26 Luke Kenneth... redo focus of virtual reg port to do only full datawidt...
2020-05-26 Michael NolanAdd extras from bottom of the file
2020-05-26 Michael NolanRewrite proof to be more in line with what appears...
2020-05-26 Luke Kenneth... sort-of (maybe) implemented a virtual port on top of...
2020-05-26 Luke Kenneth... try new variant of VirtualRegFile
2020-05-26 Luke Kenneth... use nmutil treereduce
2020-05-26 Luke Kenneth... continue virtual regfile port
2020-05-26 Luke Kenneth... whitespace, add commentary
2020-05-26 colepoirierFirst attempt at implementing block access rd and wr...
2020-05-25 Cesar StraussCheck that busy_o doesn't rise on its own
2020-05-25 Cesar StraussImplement the issue_i/busy_o protocol check.
2020-05-25 Cesar StraussMove process list to CompUnitParallelTest
2020-05-25 Michael NolanCorrect polarity of shadow signal
2020-05-25 Luke Kenneth... document shadown inversion
2020-05-25 Michael NolanAdd link to compunit wiki page
2020-05-25 Michael NolanCorrect property numbers, add assertions about busy
2020-05-25 Luke Kenneth... update comments on compalu_multi.py
2020-05-25 Michael NolanAdd assertions about go_wr and wr_rel
2020-05-25 Michael NolanMinor cleanup of comments
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