2021-07-31 |
Jonathan Neuschäfer | Don't import soc.fu.div.test.test_pipe_caller.get_cu_inputs |
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2021-07-31 |
Tobias Platen | partial fix for src/soc/experiment/compldst_multi.py |
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2021-07-30 |
Tobias Platen | partially fix unit test in compldst_multi.py |
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2021-07-26 |
Tobias Platen | compldst_multi: add debug output for dcbz |
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2021-07-24 |
Tobias Platen | add test_issuer_dcache.py |
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2021-07-23 |
Tobias Platen | ldst: cleanup debug outputs |
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2021-07-23 |
Tobias Platen | test_dcbz_pi.py: dcbz now working |
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2021-07-21 |
Tobias Platen | revert accidential delete in test_pi2ls.py causing... |
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2021-07-21 |
Tobias Platen | test_dcbz_pi.py: do not use problem state |
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2021-07-21 |
Tobias Platen | update pi_dcbz function |
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2021-07-19 |
Tobias Platen | src/soc/config/test/test_pi2ls.py: add more debug outputs |
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2021-07-19 |
Tobias Platen | test_dcbz_pi.py: more work on unit test |
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2021-07-15 |
Luke Kenneth... | update TestRunner, SVSTATE is now a class that inherits... |
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2021-07-14 |
Luke Kenneth... | update SVSTATE to 64 bit length (fortunately very easy) |
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2021-07-14 |
Tobias Platen | add more debug outputs, pass dcbz to loadstore/dcache |
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2021-07-14 |
Tobias Platen | dcache: improve debug output |
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2021-07-12 |
Luke Kenneth... | use standard create_pdecode in TestRunner |
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2021-07-12 |
Luke Kenneth... | use default decoder, do not pass one in. |
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2021-07-11 |
Tobias Platen | more work on test_dcbz_pi.py |
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2021-07-11 |
Tobias Platen | pass self.pi.is_dcbz to request |
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2021-07-11 |
Tobias Platen | implement pi_dcbz |
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2021-07-11 |
Tobias Platen | Merge branch 'master' of ssh://git.libre-riscv.org... |
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2021-07-11 |
Tobias Platen | add test_dcbz_pi.py (skeleton only) |
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2021-07-10 |
Cesar Strauss | Show some usage of PortInterface in action |
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2021-07-10 |
Cesar Strauss | Add new traces to the GTKWave document |
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2021-07-10 |
Cesar Strauss | Add operand producers to the parallel LDST Compunit... |
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2021-07-10 |
Cesar Strauss | Detect unexpected operand fetches and produced results |
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2021-07-07 |
Cesar Strauss | Start of a GTKWave document for the LDST CompUnit paral... |
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2021-07-04 |
Cesar Strauss | Beginning of a class to make a parallel test case for... |
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2021-06-30 |
Tobias Platen | cut down on time by uncommenting data not needed, addin... |
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2021-06-28 |
Tobias Platen | update ldst test case by adding precise timing |
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2021-06-24 |
Luke Kenneth... | propagate new use_svp64_ldst_dec mode through TestCore... |
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2021-06-24 |
Luke Kenneth... | add an explicit PowerDecoder.is_svp64_mode flag to... |
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2021-06-20 |
Tobias Platen | dcache: add debug output |
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2021-06-20 |
Tobias Platen | update test_ldst_pi.py |
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2021-06-18 |
Tobias Platen | uncomment test_dcache_random |
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2021-06-18 |
Tobias Platen | src/soc/fu/ldst/loadstore.py: keep data for the whole... |
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2021-06-14 |
Tobias Platen | update testcase for ldst |
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2021-06-10 |
Luke Kenneth... | whoops Popcount datalen too big (wasted bits). reduce |
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2021-06-09 |
Luke Kenneth... | git submodule update |
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2021-06-09 |
Luke Kenneth... | disconnect pll clock, connected in peripheral interconnect |
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2021-06-09 |
Luke Kenneth... | add in/out of ref_clk and pllclk_clk when PLL enabled |
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2021-06-06 |
Cesar Strauss | Start a new self-contained test suite for LDSTCompUnit |
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2021-06-03 |
Luke Kenneth... | comment out domains that have already been created |
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2021-06-03 |
Luke Kenneth... | no, do not assign clock to clock! |
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2021-06-03 |
Luke Kenneth... | rename ref to ref_v in PLL due to ref being a verilog... |
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2021-06-03 |
Luke Kenneth... | sort out PLL domains but bypass PLL due to lack of... |
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2021-06-03 |
Luke Kenneth... | use DomainRenamer on all sub-components of TestIssuer |
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2021-06-03 |
Luke Kenneth... | make core_rst a member of TestIssuerInternal |
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2021-06-01 |
Tobias Platen | test_ldst_pi.py: add new test case |
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2021-05-29 |
Tobias Platen | test_ldst_pi.py: first version of test_dcache_random() |
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2021-05-29 |
Tobias Platen | test_ldst_pi.py: more test_dcache_regression() |
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2021-05-27 |
Luke Kenneth... | adjust PLL connections looking for coriolis2 issue |
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2021-05-27 |
Luke Kenneth... | corrections on spblock ack |
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2021-05-27 |
Luke Kenneth... | classic wishbone mode: must not do ack if already acked |
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2021-05-26 |
Luke Kenneth... | arse. PLL test_issuer clk_sel_i accidentally only 1... |
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2021-05-26 |
Luke Kenneth... | remove err feature from sram4k wb |
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2021-05-26 |
Luke Kenneth... | add ldst PortInterface misalign unit test (underway) |
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2021-05-26 |
Luke Kenneth... | rename PLL signals |
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2021-05-25 |
Tobias Platen | test_ldst_pi.py: fix race condition causing early stop |
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2021-05-25 |
Tobias Platen | wait_ldok: add debug output count |
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2021-05-24 |
Luke Kenneth... | whoops sort out name of SPBlock RAM |
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2021-05-24 |
Luke Kenneth... | change name of submodule to real_pll |
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2021-05-24 |
Luke Kenneth... | match up PLL names |
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2021-05-22 |
Cesar Strauss | Remove redundant build step |
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2021-05-22 |
Cesar Strauss | Include missing step in automated build |
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2021-05-22 |
Cesar Strauss | Move the reset code outside of the sub-test |
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2021-05-22 |
Luke Kenneth... | update submodule |
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2021-05-22 |
Luke Kenneth... | update PLL to use Instance |
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2021-05-15 |
Tobias Platen | test_ldst_pi.py: add dcache regression and random test... |
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2021-05-14 |
Luke Kenneth... | add radix MMU "miss" test |
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2021-05-14 |
Luke Kenneth... | clear out request data on return to idle |
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2021-05-14 |
Luke Kenneth... | sort out LoadStore1 misalignment FSM, also required... |
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2021-05-14 |
Luke Kenneth... | remove minerva units previously missed in cleanout |
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2021-05-14 |
Luke Kenneth... | add misaligned load through MMU (which is incorrectly... |
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2021-05-13 |
Luke Kenneth... | minor rework of wb_get, make generic |
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2021-05-13 |
Luke Kenneth... | added STORE test in test_ldst_pi.py, and it worked... |
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2021-05-13 |
Luke Kenneth... | update comments in issuer.py regarding a 4th FSM |
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2021-05-13 |
Luke Kenneth... | yet more debug log stuff for DCache, this time on Cache... |
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2021-05-13 |
Luke Kenneth... | fix wb_get error where data was being corrupted |
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2021-05-13 |
Luke Kenneth... | add read at different locations in test_ldst_pi.py |
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2021-05-13 |
Luke Kenneth... | add some data for MMU to actually look up |
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2021-05-13 |
Luke Kenneth... | ha, hilarious: swapped TLBUpdate output sizes db_out... |
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2021-05-13 |
Luke Kenneth... | whoops TLBIE must *clear* the valid bit not set it... |
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2021-05-13 |
Luke Kenneth... | more debug Display in dcache.py |
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2021-05-13 |
Luke Kenneth... | putting in a lot more debug print statements in DCache... |
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2021-05-12 |
Luke Kenneth... | add dcache tlb / pte test |
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2021-05-12 |
Luke Kenneth... | set m_out.load from ldst_r(egister) in LoadStore1 |
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2021-05-12 |
Luke Kenneth... | move dcache unit test to separate test_dcache.py |
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2021-05-12 |
Luke Kenneth... | experimentation with MMU-enabled LoadStore1 through... |
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2021-05-12 |
Luke Kenneth... | add debug info, update comments, disable dcache in... |
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2021-05-12 |
Luke Kenneth... | start doing virtual memory queries via PortInterface... |
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2021-05-12 |
Luke Kenneth... | whoops missing default zero (no idea how) |
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2021-05-12 |
Luke Kenneth... | addcomments for MMU PortInterface test (how it, um... |
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2021-05-12 |
Luke Kenneth... | bit of a hack to get test_mmu_dcache_pi.py operational. |
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2021-05-12 |
Luke Kenneth... | whitespace |
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2021-05-12 |
Luke Kenneth... | no need for sel0 |
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2021-05-11 |
Luke Kenneth... | pass through MSR.PR through PortInterface, into LoadStore1 |
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2021-05-11 |
Luke Kenneth... | connect MSR.PR to PortInterface in LDSTCompUnit |
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2021-05-11 |
Luke Kenneth... | add msr_pr bit in PortInterface |
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