| 2020-08-27 | 
Luke Kenneth...  | xer so is not being passed through to CR0 | 
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| 2020-08-27 | 
Luke Kenneth...  | really bad hack to fix simulator bug in carry handling | 
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| 2020-08-27 | 
Luke Kenneth...  | augment addme test case to show bug #476 | 
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| 2020-08-27 | 
Luke Kenneth...  | add addze and addme uni tests | 
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| 2020-08-27 | 
Luke Kenneth...  | incompatibility with POWER9 on mulhw/u due to lack...  | 
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| 2020-08-27 | 
Luke Kenneth...  | overflow-enable does not occur on shift operations | 
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| 2020-08-27 | 
Luke Kenneth...  | oink, write_cr shiftrot record width was zero (??) | 
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| 2020-08-27 | 
Luke Kenneth...  | sorting out shift_rot to use new output stage data...  | 
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| 2020-08-27 | 
Luke Kenneth...  | need to read SO if Rc=1 | 
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| 2020-08-27 | 
Luke Kenneth...  | reorg of SO handling related to CR0 | 
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| 2020-08-26 | 
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc | 
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| 2020-08-26 | 
Cole Poirier | dcache.py replace subtypes/types/constant aliases with...  | 
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| 2020-08-26 | 
Luke Kenneth...  | use sub-test in logical test_pipe_caller | 
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| 2020-08-26 | 
Luke Kenneth...  | investigating div fsm and simulator bug | 
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| 2020-08-25 | 
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc | 
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| 2020-08-25 | 
Cole Poirier | dcache.py rearrange, transform classes into functions...  | 
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| 2020-08-25 | 
Jacob Lifshay | fix broken remainder for div FSM | 
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| 2020-08-25 | 
Jacob Lifshay | clean up formatting | 
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| 2020-08-25 | 
Luke Kenneth...  | although shift-rot does not alter XER.so it still needs...  | 
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| 2020-08-25 | 
Luke Kenneth...  | add way to capture CR from DMI in litex sim | 
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| 2020-08-25 | 
Luke Kenneth...  | add CR read to DMI interface | 
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| 2020-08-25 | 
Luke Kenneth...  | shorten using temp vars | 
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| 2020-08-25 | 
Luke Kenneth...  | add CR DMI interface | 
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| 2020-08-25 | 
Luke Kenneth...  | add crxor unit test to qemu | 
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| 2020-08-25 | 
Cole Poirier | dcache.py fix whitespace, fomatting, syntax | 
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| 2020-08-25 | 
Cole Poirier | dcache.py fix formatting | 
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| 2020-08-25 | 
Cole Poirier | dcache.py move Reservation RecordObject to top of file | 
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| 2020-08-25 | 
Cole Poirier | dcache.py move RegStage1 RecordObject to top of file | 
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| 2020-08-25 | 
Cole Poirier | dcache.py move MemAccessRequest RecordObject to top...  | 
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| 2020-08-25 | 
Cole Poirier | dcache.py move Stage0 RecordObject to top of file | 
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| 2020-08-24 | 
Luke Kenneth...  | argh, reading regfile over DMI was overlapped and corru...  | 
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| 2020-08-24 | 
Luke Kenneth...  | add isel CR tests to run on qemu (confirmed working) | 
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| 2020-08-24 | 
Tobias Platen | TestCachedMemoryPortInterface cleanup | 
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| 2020-08-24 | 
Luke Kenneth...  | make it easier to select FSM/Pipe DIV unit | 
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| 2020-08-24 | 
Luke Kenneth...  | fix *another* ld-update-related timing / FSM issue | 
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| 2020-08-24 | 
Luke Kenneth...  | tidyup / shuffle after review | 
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| 2020-08-24 | 
Luke Kenneth...  | remove default parameter | 
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| 2020-08-24 | 
Luke Kenneth...  | "WAY" does not exist - range(NUM_WAYS) was intended | 
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| 2020-08-24 | 
Luke Kenneth...  | use WAY_BITS in appropriate locations | 
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| 2020-08-24 | 
Luke Kenneth...  | reminder that the license (reflecting what is in setup...  | 
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| 2020-08-24 | 
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc | 
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| 2020-08-24 | 
Cole Poirier | dcache.py commit first full tranlation pass, about...  | 
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| 2020-08-23 | 
Luke Kenneth...  | update copyright notices to include additional primary...  | 
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| 2020-08-23 | 
Luke Kenneth...  | add load algebraic immediate unit test | 
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| 2020-08-23 | 
Luke Kenneth...  | add algebraic ld tests lwax, lwaux | 
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| 2020-08-23 | 
Michael Nolan | Add copyright to files I primarily authored in simulator/ | 
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| 2020-08-23 | 
Michael Nolan | Add copyright to files in fu/ that I was the primary...  | 
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| 2020-08-23 | 
Michael Nolan | Add copyright statement to power_decoder.py | 
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| 2020-08-23 | 
Luke Kenneth...  | bring "core stopped" signal out through DMI interface | 
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| 2020-08-23 | 
Luke Kenneth...  | add in DMI "stat" loop which monitors core "stopping" | 
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| 2020-08-23 | 
Cesar Strauss | Allow an empty style, and passing default styles as...  | 
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| 2020-08-23 | 
Cesar Strauss | Add comment node type | 
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| 2020-08-23 | 
Cesar Strauss | Add base and display styles | 
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| 2020-08-23 | 
Cesar Strauss | Apply style from node own name | 
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| 2020-08-23 | 
Cesar Strauss | Add color style | 
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| 2020-08-23 | 
Cesar Strauss | Collect styles from the tuple | 
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| 2020-08-23 | 
Cesar Strauss | Propagate the root style to all signals | 
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| 2020-08-23 | 
Luke Kenneth...  | comment why litex sim mem map is altered | 
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| 2020-08-23 | 
Luke Kenneth...  | multiply does not have invert_in, zero_a or invert_out | 
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| 2020-08-22 | 
Luke Kenneth...  | rename invert_a to invert_in because logical inverts RB | 
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| 2020-08-22 | 
Luke Kenneth...  | update submodule | 
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| 2020-08-22 | 
Luke Kenneth...  | load bios not 1.bin unit test | 
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| 2020-08-22 | 
Luke Kenneth...  | add extra div regression tests | 
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| 2020-08-22 | 
Cesar Strauss | Move comments to the docstring | 
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| 2020-08-22 | 
Cesar Strauss | Walk the DOM and emit the trace names | 
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| 2020-08-22 | 
Luke Kenneth...  | add eqv to logical unit test | 
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| 2020-08-22 | 
Luke Kenneth...  | add nor and nand to unit test | 
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| 2020-08-22 | 
Luke Kenneth...  | moved to div pipe temporarily in compunits | 
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| 2020-08-22 | 
Luke Kenneth...  | bug in andc and orc, complement was taking place on...  | 
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| 2020-08-22 | 
Luke Kenneth...  | extend addis test | 
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| 2020-08-22 | 
Luke Kenneth...  | add andc and orc tests, failing because RB needs invers...  | 
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| 2020-08-22 | 
Luke Kenneth...  | modsd bug, https://bugs.libre-soc.org/show_bug.cgi...  | 
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| 2020-08-22 | 
Cesar Strauss | First draft of a mini-language to describe GTKWave...  | 
commit | commitdiff | tree | 
| 2020-08-22 | 
Luke Kenneth...  | submodule update | 
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| 2020-08-22 | 
Luke Kenneth...  | add regression test for nonzero addis | 
commit | commitdiff | tree | 
| 2020-08-22 | 
Luke Kenneth...  | add means to run microwatt test binaries | 
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| 2020-08-22 | 
Luke Kenneth...  | r0 zero tests on addis, fails | 
commit | commitdiff | tree | 
| 2020-08-22 | 
Luke Kenneth...  | investigating litex sdrinit function | 
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| 2020-08-22 | 
Luke Kenneth...  | add pseudo-op conversion | 
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| 2020-08-22 | 
Luke Kenneth...  | add start of litex bios counter loop | 
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| 2020-08-21 | 
Luke Kenneth...  | remove extraneous comments | 
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| 2020-08-21 | 
Luke Kenneth...  | testing 64-bit wishbone bus after 32-bit *still* fails...  | 
commit | commitdiff | tree | 
| 2020-08-21 | 
Tobias Platen | typo fix in test_l0_cache_buffer2.py | 
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| 2020-08-21 | 
Cole Poirier | dcache.py fix asserts, use backslash and two strings...  | 
commit | commitdiff | tree | 
| 2020-08-21 | 
Cole Poirier | dcache.py replace functions that return signals with...  | 
commit | commitdiff | tree | 
| 2020-08-21 | 
Cole Poirier | wb_types fix typo | 
commit | commitdiff | tree | 
| 2020-08-21 | 
Tobias Platen | connect TestCachedMemoryPortInterface to LDSTSplitter | 
commit | commitdiff | tree | 
| 2020-08-21 | 
Luke Kenneth...  | get litex sim enabled with 32-bit wishbone bus | 
commit | commitdiff | tree | 
| 2020-08-21 | 
Luke Kenneth...  | ld/st bus reduction test operational | 
commit | commitdiff | tree | 
| 2020-08-21 | 
Luke Kenneth...  | first test of down-converted load/store from 64 to...  | 
commit | commitdiff | tree | 
| 2020-08-21 | 
Luke Kenneth...  | first test of down-converted load/store from 64 to...  | 
commit | commitdiff | tree | 
| 2020-08-21 | 
Luke Kenneth...  | add in WishboneDownConvert into LoadStoreUnitInterface | 
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| 2020-08-21 | 
Luke Kenneth...  | comment formatting | 
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| 2020-08-21 | 
Luke Kenneth...  | remove default values | 
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| 2020-08-21 | 
Luke Kenneth...  | just range(the_constant) | 
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| 2020-08-21 | 
Samuel A. Falvo II | MUL pipeline WIP: mullw and mullwu covered. | 
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| 2020-08-21 | 
Samuel A. Falvo II | MUL pipeline: account for overflow flags.  WIP | 
commit | commitdiff | tree | 
| 2020-08-21 | 
Cole Poirier | Merge branch 'master' of git.libre-soc.org:soc | 
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| 2020-08-21 | 
Cole Poirier | dcache.py commit today and yesterday's progress (sorry...  | 
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| 2020-08-21 | 
Samuel A. Falvo II | MUL pipeline proofs: mulli / mullw WIP. | 
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| next |