soc.git
2020-07-02 Luke Kenneth... name function unit ALUs
2020-07-02 Luke Kenneth... comment out DIV unit for now
2020-07-02 Luke Kenneth... increase combinatorial stages to 8
2020-07-02 Luke Kenneth... reduce DIV radix to 1
2020-07-02 Luke Kenneth... add DIV function unit to compunits
2020-07-02 Luke Kenneth... add trap function unit into compunits
2020-07-02 Luke Kenneth... add bare wishbone option to TestIssuer, sort out ports
2020-07-02 Luke Kenneth... use single-arg pspec for TestIssuer and Core
2020-07-02 Luke Kenneth... first experimental index.rst for sphinx documentation
2020-07-02 Luke Kenneth... add sphinx doc preliminary start
2020-07-02 Cesar StraussPresent the ALU result only when valid_o is active
2020-07-01 Luke Kenneth... whoops missed some cases in unit test changing ALUHelpers
2020-07-01 Luke Kenneth... minor reorg on how Bus and Config classes are set up
2020-07-01 Luke Kenneth... whoops swapped trap test instructions accidentally
2020-07-01 Luke Kenneth... print out msr for debug
2020-07-01 Luke Kenneth... attempting to add SPRs to rfid test
2020-07-01 Luke Kenneth... add OP_SC
2020-07-01 Luke Kenneth... trap test check results
2020-07-01 Luke Kenneth... add name "test_issuer" to ilang conversion
2020-07-01 Luke Kenneth... add in trap compunit
2020-07-01 Luke Kenneth... add rfid and td/tw trap test
2020-07-01 Luke Kenneth... continue debugging trap pipeline
2020-07-01 Luke Kenneth... debugging trap pipeline
2020-07-01 Luke Kenneth... start running trap unit test, fixing errors
2020-06-30 Luke Kenneth... add lte ltu for use by twi and other trap functions
2020-06-30 Luke Kenneth... add in pseudocode keyword into mdwn isa files
2020-06-30 Luke Kenneth... code-morph on div pipeline
2020-06-29 Luke Kenneth... add README for fu directory
2020-06-29 Luke Kenneth... use correct ALUHelpers in div test
2020-06-29 Luke Kenneth... sort out syntax errors in div
2020-06-29 Luke Kenneth... first unit test for div
2020-06-29 Luke Kenneth... update submodule to fix div bug
2020-06-29 Luke Kenneth... add ignore for parsetab.py
2020-06-29 Luke Kenneth... add autogenerated do not commit comment
2020-06-29 Luke Kenneth... update submodule to div overflow
2020-06-29 Luke Kenneth... separate out divide by zero cases
2020-06-29 Luke Kenneth... update OV and OV32 ISACaller flags if overflow occurs
2020-06-29 Luke Kenneth... attempting to add overflow setting in ISACaller
2020-06-29 Luke Kenneth... whoops, hex parser digits are in multiples of 4 bits
2020-06-29 Luke Kenneth... fetch instructions from bare wishbone fetch unit
2020-06-28 Cesar StraussStart with a simpler test case
2020-06-28 Cesar StraussLet p.ready_o be active while the test ALU is idle
2020-06-28 Luke Kenneth... add cached fetch unit pass-through args
2020-06-28 Luke Kenneth... need args to WishboneArbiter, match data width size
2020-06-28 Cesar StraussAdd missing ports to the test ALU
2020-06-28 Luke Kenneth... read from instruction memory using FetchUnitInterface
2020-06-28 Luke Kenneth... add Config Fetch interface and quick unit test
2020-06-28 Luke Kenneth... add test instruction memory
2020-06-28 Luke Kenneth... add readonly option to TestMemory
2020-06-28 Luke Kenneth... expand instruction bus width to 64 bit, start on a...
2020-06-28 Luke Kenneth... parameterise minerva i-cache
2020-06-28 Luke Kenneth... got Pi2LSUI FSM working
2020-06-28 Luke Kenneth... sram address do not cut by LSBs
2020-06-28 Luke Kenneth... new Pi2LSUI working, using PortInterfaceBase
2020-06-28 Luke Kenneth... start new version of Pi2LSUI based on PortInterfaceBase
2020-06-28 Luke Kenneth... pass addr/mask through to PortInterfaceBase rd/wr addr
2020-06-28 Luke Kenneth... cleanup (remove unneeded imports)
2020-06-28 Luke Kenneth... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth... more code-shuffle for TestMemoryPortInterface
2020-06-28 Luke Kenneth... minor cleanup, put get/set rdport/wrport into function
2020-06-28 Luke Kenneth... merge LDSTPort into TestMemoryPortInterface
2020-06-28 Luke Kenneth... use PortInterface connect_port
2020-06-28 Luke Kenneth... use PortInterface connect_port
2020-06-28 Luke Kenneth... attempt to get Pi2LSUI FSM working
2020-06-27 Luke Kenneth... only activate ld_in_progress if addr is ok
2020-06-27 Luke Kenneth... make Memory accessible via TestSRAMBareLoadStoreUnit
2020-06-27 Luke Kenneth... increase (double) address width in TstL0CacheBuffer
2020-06-27 Luke Kenneth... increase (double) address width in TstL0CacheBuffer
2020-06-27 Luke Kenneth... unit test in l0_cache to connect to testpi and test_bare_wb
2020-06-27 Luke Kenneth... make PortInterface modules consistent with same API
2020-06-27 Luke Kenneth... use ConfigMemoryPortInterface in TstL0CacheBuffer
2020-06-27 Luke Kenneth... fix TestMemLoadStoreUnit, it required a FSM to monitor...
2020-06-27 Luke Kenneth... add wishbone Pi2LSUI test
2020-06-27 Luke Kenneth... reconfigureable PortInterface testing now possible
2020-06-26 Luke Kenneth... name issue in Pi2LSUI
2020-06-26 Luke Kenneth... whitespace and imports
2020-06-26 Luke Kenneth... whitespace
2020-06-26 Luke Kenneth... slight reorg on test_pi2ls.py
2020-06-26 Luke Kenneth... correct address in pi2ls
2020-06-26 Luke Kenneth... oops forgot to initialise base class of TestMemLoadStor...
2020-06-26 Luke Kenneth... add in LenExpand shift/mask
2020-06-26 Luke Kenneth... add quick test showing Pi2LSUI not quite reading/writing to
2020-06-26 Luke Kenneth... remove extraneous yields
2020-06-26 Michael NolanModify pi2ls so it passes the portinterface unit tests
2020-06-26 Luke Kenneth... set address ok and fix unit test to check it properly
2020-06-26 Luke Kenneth... add pi.busy_o connection, increase to 64 bit
2020-06-26 Luke Kenneth... unit test broken is ok :)
2020-06-26 Luke Kenneth... set pi.ld.ok to 1 if pi.is_ld_i is set
2020-06-26 Michael NolanMove tests for pimem to new file, add ability to test...
2020-06-26 Luke Kenneth... load/store unit test needed to wait for busy_o
2020-06-26 Luke Kenneth... whitespace
2020-06-26 Luke Kenneth... clean up output from BareLoadStoreUnit
2020-06-26 Luke Kenneth... halve the test memory size again
2020-06-26 Luke Kenneth... shrink test memory size down to only 64 words
2020-06-26 Luke Kenneth... investigating why write-enable not getting passed through
2020-06-26 Luke Kenneth... whoops forgot to call parent elaborate
2020-06-26 Luke Kenneth... add test of SRAM through wishbone bus
2020-06-26 Luke Kenneth... code-morph which redirects lsmem unit test through...
2020-06-26 Luke Kenneth... add a test SRAM that lives behind a minerva LoadStoreUn...
2020-06-26 Luke Kenneth... dynamically specify wishbone layout (no longer hardcode...
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