soc.git
2020-08-25 Cole Poirierdcache.py fix formatting
2020-08-25 Cole Poirierdcache.py move Reservation RecordObject to top of file
2020-08-25 Cole Poirierdcache.py move RegStage1 RecordObject to top of file
2020-08-25 Cole Poirierdcache.py move MemAccessRequest RecordObject to top...
2020-08-25 Cole Poirierdcache.py move Stage0 RecordObject to top of file
2020-08-24 Luke Kenneth... argh, reading regfile over DMI was overlapped and corru...
2020-08-24 Luke Kenneth... add isel CR tests to run on qemu (confirmed working)
2020-08-24 Tobias PlatenTestCachedMemoryPortInterface cleanup
2020-08-24 Luke Kenneth... make it easier to select FSM/Pipe DIV unit
2020-08-24 Luke Kenneth... fix *another* ld-update-related timing / FSM issue
2020-08-24 Luke Kenneth... tidyup / shuffle after review
2020-08-24 Luke Kenneth... remove default parameter
2020-08-24 Luke Kenneth... "WAY" does not exist - range(NUM_WAYS) was intended
2020-08-24 Luke Kenneth... use WAY_BITS in appropriate locations
2020-08-24 Luke Kenneth... reminder that the license (reflecting what is in setup...
2020-08-24 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-24 Cole Poirierdcache.py commit first full tranlation pass, about...
2020-08-23 Luke Kenneth... update copyright notices to include additional primary...
2020-08-23 Luke Kenneth... add load algebraic immediate unit test
2020-08-23 Luke Kenneth... add algebraic ld tests lwax, lwaux
2020-08-23 Michael NolanAdd copyright to files I primarily authored in simulator/
2020-08-23 Michael NolanAdd copyright to files in fu/ that I was the primary...
2020-08-23 Michael NolanAdd copyright statement to power_decoder.py
2020-08-23 Luke Kenneth... bring "core stopped" signal out through DMI interface
2020-08-23 Luke Kenneth... add in DMI "stat" loop which monitors core "stopping"
2020-08-23 Cesar StraussAllow an empty style, and passing default styles as...
2020-08-23 Cesar StraussAdd comment node type
2020-08-23 Cesar StraussAdd base and display styles
2020-08-23 Cesar StraussApply style from node own name
2020-08-23 Cesar StraussAdd color style
2020-08-23 Cesar StraussCollect styles from the tuple
2020-08-23 Cesar StraussPropagate the root style to all signals
2020-08-23 Luke Kenneth... comment why litex sim mem map is altered
2020-08-23 Luke Kenneth... multiply does not have invert_in, zero_a or invert_out
2020-08-22 Luke Kenneth... rename invert_a to invert_in because logical inverts RB
2020-08-22 Luke Kenneth... update submodule
2020-08-22 Luke Kenneth... load bios not 1.bin unit test
2020-08-22 Luke Kenneth... add extra div regression tests
2020-08-22 Cesar StraussMove comments to the docstring
2020-08-22 Cesar StraussWalk the DOM and emit the trace names
2020-08-22 Luke Kenneth... add eqv to logical unit test
2020-08-22 Luke Kenneth... add nor and nand to unit test
2020-08-22 Luke Kenneth... moved to div pipe temporarily in compunits
2020-08-22 Luke Kenneth... bug in andc and orc, complement was taking place on...
2020-08-22 Luke Kenneth... extend addis test
2020-08-22 Luke Kenneth... add andc and orc tests, failing because RB needs invers...
2020-08-22 Luke Kenneth... modsd bug, https://bugs.libre-soc.org/show_bug.cgi...
2020-08-22 Cesar StraussFirst draft of a mini-language to describe GTKWave...
2020-08-22 Luke Kenneth... submodule update
2020-08-22 Luke Kenneth... add regression test for nonzero addis
2020-08-22 Luke Kenneth... add means to run microwatt test binaries
2020-08-22 Luke Kenneth... r0 zero tests on addis, fails
2020-08-22 Luke Kenneth... investigating litex sdrinit function
2020-08-22 Luke Kenneth... add pseudo-op conversion
2020-08-22 Luke Kenneth... add start of litex bios counter loop
2020-08-21 Luke Kenneth... remove extraneous comments
2020-08-21 Luke Kenneth... testing 64-bit wishbone bus after 32-bit *still* fails...
2020-08-21 Tobias Platentypo fix in test_l0_cache_buffer2.py
2020-08-21 Cole Poirierdcache.py fix asserts, use backslash and two strings...
2020-08-21 Cole Poirierdcache.py replace functions that return signals with...
2020-08-21 Cole Poirierwb_types fix typo
2020-08-21 Tobias Platenconnect TestCachedMemoryPortInterface to LDSTSplitter
2020-08-21 Luke Kenneth... get litex sim enabled with 32-bit wishbone bus
2020-08-21 Luke Kenneth... ld/st bus reduction test operational
2020-08-21 Luke Kenneth... first test of down-converted load/store from 64 to...
2020-08-21 Luke Kenneth... first test of down-converted load/store from 64 to...
2020-08-21 Luke Kenneth... add in WishboneDownConvert into LoadStoreUnitInterface
2020-08-21 Luke Kenneth... comment formatting
2020-08-21 Luke Kenneth... remove default values
2020-08-21 Luke Kenneth... just range(the_constant)
2020-08-21 Samuel A. Falvo IIMUL pipeline WIP: mullw and mullwu covered.
2020-08-21 Samuel A. Falvo IIMUL pipeline: account for overflow flags. WIP
2020-08-21 Cole PoirierMerge branch 'master' of git.libre-soc.org:soc
2020-08-21 Cole Poirierdcache.py commit today and yesterday's progress (sorry...
2020-08-21 Samuel A. Falvo IIMUL pipeline proofs: mulli / mullw WIP.
2020-08-20 Samuel A. Falvo IIMUL pipeline proof: muldw(u)
2020-08-20 Samuel A. Falvo IIMUL pipeline proof: signed mulhw
2020-08-20 Tobias Platenstart wiring TestCachedMemoryPortInterface
2020-08-20 Tobias Platentestcase refactoring
2020-08-20 Tobias Platenadd new class TestCachedMemoryPortInterface
2020-08-20 Luke Kenneth... bugfix wishbone downconvert using wb sram 64-to-32...
2020-08-20 Luke Kenneth... add a wishbone upconverter
2020-08-19 Luke Kenneth... rename and document fields in shift_rot proof
2020-08-19 Luke Kenneth... comments in dcache
2020-08-19 Luke Kenneth... more subtle interactions between wishbone bus when...
2020-08-19 Luke Kenneth... bit of a reorg of mul proof, tracking down missing
2020-08-19 Luke Kenneth... move long mul tests to separate unit test
2020-08-19 Luke Kenneth... use "Mask" class which is more gate-efficient than...
2020-08-19 Samuel A. Falvo IIWIP: OP_MUL proofs started.
2020-08-19 Luke Kenneth... set up StageChain of 3 mul stages
2020-08-18 Cole Poirierfu/mul/test/test_pipe_caller.py test case_all_rb_close_...
2020-08-18 Tobias Platenadd testcase for LDSTSplitter using PortInterface
2020-08-18 Luke Kenneth... fix spr state test
2020-08-18 Luke Kenneth... add comment in dcache.py
2020-08-17 Cole Poirierdcache.py commit today's progress on translating dcache...
2020-08-17 Cole PoirierCreate file experiment/wb_types.py to mirror microwatt...
2020-08-17 Luke Kenneth... move Mask to nmutil
2020-08-17 Luke Kenneth... turn SelectableInt less/greater into signed versions.
2020-08-17 Luke Kenneth... use longer memtest in litex sim
2020-08-17 Luke Kenneth... adjust litex bios cmp test
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