Allow the formal engine to perform a same-cycle result in the ALU
[soc.git] / src / soc / fu / alu / pipe_data.py
1 from soc.fu.alu.alu_input_record import CompALUOpSubset
2 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
3
4
5 class ALUInputData(IntegerData):
6 regspec = [('INT', 'ra', '0:63'), # RA
7 ('INT', 'rb', '0:63'), # RB/immediate
8 ('XER', 'xer_so', '32'), # XER bit 32: SO
9 ('XER', 'xer_ca', '34,45')] # XER bit 34/45: CA/CA32
10 def __init__(self, pspec):
11 super().__init__(pspec, False)
12 # convenience
13 self.a, self.b = self.ra, self.rb
14
15
16 class ALUOutputData(IntegerData):
17 regspec = [('INT', 'o', '0:63'),
18 ('CR', 'cr_a', '0:3'),
19 ('XER', 'xer_ca', '34,45'), # bit0: ca, bit1: ca32
20 ('XER', 'xer_ov', '33,44'), # bit0: ov, bit1: ov32
21 ('XER', 'xer_so', '32')]
22 def __init__(self, pspec):
23 super().__init__(pspec, True)
24 # convenience
25 self.cr0 = self.cr_a
26
27
28 class ALUPipeSpec(CommonPipeSpec):
29 regspec = (ALUInputData.regspec, ALUOutputData.regspec)
30 opsubsetkls = CompALUOpSubset