add register specs to pipeline in/out so that they can be used to connect up
[soc.git] / src / soc / fu / branch / pipe_data.py
1 """
2 Optional Register allocation listed below. mandatory input
3 (CompBROpSubset, CIA) not included.
4
5 * CR is Condition Register (not an SPR)
6 * SPR1 and SPR2 are all from the SPR regfile. 2 ports are needed
7
8 insn CR SPR1 SPR2
9 ---- -- ---- ----
10 op_b xx xx xx
11 op_ba xx xx xx
12 op_bl xx xx xx
13 op_bla xx xx xx
14 op_bc CR, xx, CTR
15 op_bca CR, xx, CTR
16 op_bcl CR, xx, CTR
17 op_bcla CR, xx, CTR
18 op_bclr CR, LR, CTR
19 op_bclrl CR, LR, CTR
20 op_bcctr CR, xx, CTR
21 op_bcctrl CR, xx, CTR
22 op_bctar CR, TAR, CTR
23 op_bctarl CR, TAR, CTR
24 """
25
26 from nmigen import Signal, Const
27 from ieee754.fpcommon.getop import FPPipeContext
28 from soc.decoder.power_decoder2 import Data
29 from soc.fu.alu.pipe_data import IntegerData
30
31
32 class BranchInputData(IntegerData):
33 regspec = [('SPR', 'spr1', '0:63'),
34 ('SPR', 'spr2', '0:63'),
35 ('CR', 'cr', '32'),
36 ('PC', 'cia', '0:63')]
37 def __init__(self, pspec):
38 super().__init__(pspec)
39 # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
40 # this involves the *decode* unit selecting the register, based
41 # on detecting the operand being bcctr, bclr or bctar
42
43 self.spr1 = Signal(64, reset_less=True) # see table above, SPR1
44 self.spr2 = Signal(64, reset_less=True) # see table above, SPR2
45 self.cr = Signal(32, reset_less=True) # Condition Register(s) CR0-7
46 self.cia = Signal(64, reset_less=True) # Current Instruction Address
47
48 # convenience variables. not all of these are used at once
49 self.ctr = self.srr0 = self.hsrr0 = self.spr2
50 self.lr = self.tar = self.srr1 = self.hsrr1 = self.spr1
51
52 def __iter__(self):
53 yield from super().__iter__()
54 yield self.spr1
55 yield self.spr2
56 yield self.cr
57 yield self.cia
58
59 def eq(self, i):
60 lst = super().eq(i)
61 return lst + [self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
62 self.cr.eq(i.cr), self.cia.eq(i.cia)]
63
64
65 class BranchOutputData(IntegerData):
66 regspec = [('SPR', 'spr1', '0:63'),
67 ('SPR', 'spr2', '0:63'),
68 ('PC', 'cia', '0:63')]
69 def __init__(self, pspec):
70 super().__init__(pspec)
71 self.spr1 = Data(64, name="spr1")
72 self.spr2 = Data(64, name="spr2")
73 self.nia = Data(64, name="nia")
74
75 # convenience variables.
76 self.lr = self.tar = self.spr1
77 self.ctr = self.spr2
78
79 def __iter__(self):
80 yield from super().__iter__()
81 yield from self.spr1
82 yield from self.spr2
83 yield from self.nia
84
85 def eq(self, i):
86 lst = super().eq(i)
87 return lst + [self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
88 self.nia.eq(i.nia)]