2 Optional Register allocation listed below. mandatory input
3 (CompBROpSubset, CIA) not included.
5 * CR is Condition Register (not an SPR)
6 * SPR1 and SPR2 are all from the SPR regfile. 2 ports are needed
23 op_bctarl CR, TAR, CTR
26 from nmigen
import Signal
, Const
27 from ieee754
.fpcommon
.getop
import FPPipeContext
28 from soc
.decoder
.power_decoder2
import Data
29 from soc
.fu
.alu
.pipe_data
import IntegerData
32 class BranchInputData(IntegerData
):
33 regspec
= [('SPR', 'spr1', '0:63'),
34 ('SPR', 'spr2', '0:63'),
36 ('PC', 'cia', '0:63')]
37 def __init__(self
, pspec
):
38 super().__init
__(pspec
)
39 # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
40 # this involves the *decode* unit selecting the register, based
41 # on detecting the operand being bcctr, bclr or bctar
43 self
.spr1
= Signal(64, reset_less
=True) # see table above, SPR1
44 self
.spr2
= Signal(64, reset_less
=True) # see table above, SPR2
45 self
.cr
= Signal(32, reset_less
=True) # Condition Register(s) CR0-7
46 self
.cia
= Signal(64, reset_less
=True) # Current Instruction Address
48 # convenience variables. not all of these are used at once
49 self
.ctr
= self
.srr0
= self
.hsrr0
= self
.spr2
50 self
.lr
= self
.tar
= self
.srr1
= self
.hsrr1
= self
.spr1
53 yield from super().__iter
__()
61 return lst
+ [self
.spr1
.eq(i
.spr1
), self
.spr2
.eq(i
.spr2
),
62 self
.cr
.eq(i
.cr
), self
.cia
.eq(i
.cia
)]
65 class BranchOutputData(IntegerData
):
66 regspec
= [('SPR', 'spr1', '0:63'),
67 ('SPR', 'spr2', '0:63'),
68 ('PC', 'cia', '0:63')]
69 def __init__(self
, pspec
):
70 super().__init
__(pspec
)
71 self
.spr1
= Data(64, name
="spr1")
72 self
.spr2
= Data(64, name
="spr2")
73 self
.nia
= Data(64, name
="nia")
75 # convenience variables.
76 self
.lr
= self
.tar
= self
.spr1
80 yield from super().__iter
__()
87 return lst
+ [self
.spr1
.eq(i
.spr1
), self
.spr2
.eq(i
.spr2
),