3 * https://bugs.libre-soc.org/show_bug.cgi?id=325
4 * https://bugs.libre-soc.org/show_bug.cgi?id=344
5 * https://libre-soc.org/openpower/isa/fixedtrap/
8 from nmigen
import (Module
, Signal
, Cat
, Mux
, Const
, signed
)
9 from nmutil
.pipemodbase
import PipeModBase
10 from nmutil
.extend
import exts
11 from soc
.fu
.trap
.pipe_data
import TrapInputData
, TrapOutputData
12 from soc
.decoder
.power_enums
import InternalOp
14 from soc
.decoder
.power_fields
import DecodeFields
15 from soc
.decoder
.power_fieldsn
import SignalBitRange
18 class TrapMainStage(PipeModBase
):
19 def __init__(self
, pspec
):
20 super().__init
__(pspec
, "main")
21 self
.fields
= DecodeFields(SignalBitRange
, [self
.i
.ctx
.op
.insn
])
22 self
.fields
.create_specs()
25 return TrapInputData(self
.pspec
)
28 return TrapOutputData(self
.pspec
)
30 def elaborate(self
, platform
):
34 a_i
, b_i
= self
.i
.a
, self
.i
.b
36 # take copy of D-Form TO field
37 i_fields
= self
.fields
.FormD
38 to
= Signal(i_fields
.TO
[0:-1].shape())
39 comb
+= to
.eq(i_fields
.TO
[0:-1])
41 # signed/unsigned temporaries for RA and RB
42 a_s
= Signal(signed(64), reset_less
=True)
43 b_s
= Signal(signed(64), reset_less
=True)
45 a
= Signal(64, reset_less
=True)
46 b
= Signal(64, reset_less
=True)
48 # set up A and B comparison (truncate/sign-extend if 32 bit)
49 with m
.If(op
.is_32bit
):
50 comb
+= a_s
.eq(exts(a_i
, 32, 64))
51 comb
+= b_s
.eq(exts(b_i
, 32, 64))
52 comb
+= a
.eq(a_i
[0:32])
53 comb
+= b
.eq(b_i
[0:32])
60 # establish comparison bits
61 lt_s
= Signal(reset_less
=True)
62 gt_s
= Signal(reset_less
=True)
63 lt_u
= Signal(reset_less
=True)
64 gt_u
= Signal(reset_less
=True)
65 equal
= Signal(reset_less
=True)
67 comb
+= lt_s
.eq(a_s
< b_s
)
68 comb
+= gt_s
.eq(a_s
> b_s
)
69 comb
+= lt_u
.eq(a
< b
)
70 comb
+= gt_u
.eq(a
> b
)
71 comb
+= equal
.eq(a
== b
)
73 # They're in reverse bit order because POWER.
74 # Check V3.0B Book 1, Appendix C.6 for chart
76 comb
+= trap_bits
.eq(Cat(gt_u
, lt_u
, equal
, gt_s
, lt_s
))
78 # establish if the trap should go ahead (any tests requested in TO)
79 should_trap
= Signal()
80 comb
+= should_trap
.eq((trap_bits
& to
).any())
82 # TODO: some #defines for the bits n stuff.
85 with m
.Case(InternalOp
.OP_TRAP
):
86 with m
.If(should_trap
):
87 comb
+= self
.o
.nia
.data
.eq(0x700) # trap address
88 comb
+= self
.o
.nia
.ok
.eq(1)
89 comb
+= self
.o
.srr1
.data
.eq(self
.i
.msr
) # old MSR
90 comb
+= self
.o
.srr1
.data
[63-46].eq(1) # XXX which bit?
91 comb
+= self
.o
.srr1
.ok
.eq(1)
92 comb
+= self
.o
.srr0
.data
.eq(self
.i
.cia
) # old PC
93 comb
+= self
.o
.srr0
.ok
.eq(1)
96 with m
.Case(InternalOp
.OP_MTMSR
):
97 # TODO: some of the bits need zeroing?
99 if e_in.insn(16) = '1' then
100 -- just update EE and RI
101 ctrl_tmp.msr(MSR_EE) <= c_in(MSR_EE);
102 ctrl_tmp.msr(MSR_RI) <= c_in(MSR_RI);
104 -- Architecture says to leave out bits 3 (HV), 51 (ME)
105 -- and 63 (LE) (IBM bit numbering)
106 ctrl_tmp.msr(63 downto 61) <= c_in(63 downto 61);
107 ctrl_tmp.msr(59 downto 13) <= c_in(59 downto 13);
108 ctrl_tmp.msr(11 downto 1) <= c_in(11 downto 1);
109 if c_in(MSR_PR) = '1' then
110 ctrl_tmp.msr(MSR_EE) <= '1';
111 ctrl_tmp.msr(MSR_IR) <= '1';
112 ctrl_tmp.msr(MSR_DR) <= '1';
114 comb
+= self
.o
.msr
.data
.eq(a
)
115 comb
+= self
.o
.msr
.ok
.eq(1)
118 with m
.Case(InternalOp
.OP_MFMSR
):
119 # TODO: some of the bits need zeroing?
120 comb
+= self
.o
.o
.data
.eq(self
.i
.msr
)
121 comb
+= self
.o
.o
.ok
.eq(1)
124 with m
.Case(InternalOp
.OP_RFID
):
127 with m
.Case(InternalOp
.OP_SC
):
130 #with m.Case(InternalOp.OP_ADDPCIS):
133 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)